C8051F303-GSR Silicon Labs, C8051F303-GSR Datasheet - Page 113

• Manufacturer Part Number: C8051F303-GSR
• Description: 8-bit Microcontrollers - MCU 8KB 14Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F303-GSR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

The direction bit (R/W) occupies the least significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 13.3 illustrates a typical
SMBus transaction.
13.3.1. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see
on page
tration scheme is employed to force one master to give up the bus. The master devices continue transmit-
ting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will
be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The win-
ning master continues its transmission without interruption; the losing master becomes a slave and
receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device
always wins, and no data is lost.
SCL
SDA
114). In the event that two or more devices attempt to begin a transfer at the same time, an arbi-
START
SLA6
Slave Address + R/W
Figure 13.3. SMBus Transaction
SLA5-0
R/W
Rev. 2.9
Section “13.3.4. SCL High (SMBus Free) Timeout”
ACK
C8051F300/1/2/3/4/5
D7
Data Byte
D6-0
NACK
STOP
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