MAX11014BGTM+ Maxim Integrated, MAX11014BGTM+ Datasheet - Page 37

• Manufacturer Part Number: MAX11014BGTM+
• Description: Special Purpose Amplifiers Auto RF MESFET Amp Drain-Current Cntrlr
• Manufacturer: Maxim Integrated
• Series: MAX11014, MAX11015r

Specifications of MAX11014BGTM+

• Rohs: yes
• Common Mode Rejection Ratio (min): 90 dB
• Operating Supply Voltage: 0.5 V to 11 V
• Supply Current: 2.8 mA
• Maximum Power Dissipation: 2162.2 mW
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-48
• Available Set Gain: 13.98 dB

Set the LDAC1 bit, D5, to 1 to load the new value of
V
into both the channel 1 DAC input and output registers.
Set to 0 to load the new value of V
tion of a V
DAC input register. Set the T1COMP1/0 bits, D4 and
D3, to control the channel 1 temperature LUT. See
Table 11a. Set the KSRC1-2/1/0 bits, D2, D1, and D0 to
control the channel 1 K parameter LUT. See Table 11b
and the SRAM LUTs section.
Set the channel 1/channel 2 DAC code by writing to the
respective channel’s DAC input registers, DAC input
and output registers, or V
DAC input registers (Table 16) and use a subsequent
write to the software load DAC register (Table 21) to
control the timing of the update. Write to the DAC input
and output registers (Table 17) to set the DAC output
voltage code directly, independent of the software load
DAC register bits. Write to the V
to include LUT data in the DAC code. Writing to the
V
following equation:
where
V
DAC code.
V
nel 1/channel 2 V
Figure 20. DAC Register Format
V
DAC1
SET
DAC(CODE)
SET(CODE)
DAC CODE
registers triggers a V
(
, upon completion of a V
CHANNEL 1/CHANNEL 2 DAC
THRUDAC1/THRUDAC2)
DAC1(CODE)
V
INPUT REGISTERS:
)
(IPDAC1/IPDAC2
DAC
=
= The 12-bit DAC code written to the chan-
= The modified channel1/channel 2 12-bit
CALCULATION
V
SET CODE
SET
(
______________________________________________________________________________________
registers.
calculation, to only the channel 1
)
(
1
+
DAC(CODE)
SET
LUT K x LUT
DAC1(CODE)
SCFG REGISTER
SET
K
registers. Write to the
LDAC_ BITS
SET TO 1 IN
[ ]
REGISTER
LDAC
DAC1
registers (Table 14)
calculation by the
Automatic RF MESFET Amplifier
, upon comple-
TEMP
calculation,
[
TEMP
INPUT AND OUTPUT REGISTERS:
CHANNEL 1/CHANNEL 2 DAC
])
Drain-Current Controllers
(THRUDAC1/
THRUDAC2)
LUT
value. The KLUT data is derived from a variety of
sources, including the V
meter register value, or various ADC channels. See the
SRAM LUTs section.
LUT
two’s-complement temperature LUT value. The tempera-
ture LUT data is derived from either internal or external
temperature values.See the SRAM LUTs section.
When the KSRC_-2/KSRC_-1/KSRC_-0 bits are set to
000 and T_COMP1/T_COMP0 bits are set to 00 or 01,
the V
Note: This is a special case and will not trigger a
V
functionality should be accessed by the THRUDAC reg-
isters.
For temperature samples or sampled KLUT sources to
automatically trigger V
must be configured to provide these samples.
Therefore, the ADC conversion register (Table 19) must
have the relevant channel bits set and the ADC must be
in a suitable clocking mode, regardless of the
ADCMON bit setting.
GATE
TEMP
K
DAC(CODE)
[K] = The interpolated, fractional 12-bit KLUT
calculation unless a sample already exists. This
[TEMP] = The interpolated, fractional 12-bit
V
DAC CODE
equation simplifies to:
(
DAC(CODE)
SET
)
=
V
register value, the K para-
CHANNEL 1/ CHANNEL 2 DAC
SET CODE
OUTPUT VOLTAGE
(
calculations, the ADC
)
37