MAX3891ECB+TD Maxim Integrated, MAX3891ECB+TD Datasheet - Page 5

• Manufacturer Part Number: MAX3891ECB+TD
• Description: Serializers & Deserializers - Serdes Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX3891ECB+TD

• Rohs: yes
• Data Rate: 2.5 Gbit/s
• Input Type: LVPECL
• Output Type: LVPECL
• Number Of Inputs: 16
• Number Of Outputs: 1
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-64 EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 750
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

The MAX3891 converts 16-bit wide, 155Mbps data to
2.5Gbps serial data (Figure 2). The MAX3891 is com-
posed of a 16-bit parallel input register, a 16-bit shift
register, control and timing logic, PECL output buffers
and a frequency-synthesizing PLL, consisting of a
phase/frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and prescaler.
The PLL synthesizes an internal 2.5Gbps reference used
to clock the output shift register. This clock is generated
from the external 155.52MHz, 77.76MHz, 51.84MHz, or
38.88MHz reference-clock signal (RCLK).
The incoming parallel data is clocked into the MAX3891
on the rising transition of the parallel clock-input signal
(PCLKI). Proper operation is ensured if the parallel-input
register is latched within a window of time (t
Figure 1. Timing Diagram
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCKLO = (PCLK0+) - (PCLKO-).
*PDI I5 = D15; PDI14 = D14, . . . PDI0 = D0.
THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN
PARALLEL INPUT DATA AND SERIAL OUTPUT DATA.
16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET,
with Clock Synthesis and LVPECL Inputs
INPUT DATA
_______________________________________________________________________________________
PARALLEL
PCLKO
(PDI_)
PCLKI
Detailed Description
t
SU
t
SKEW
t
H
SKEW
),
defined with respect to the parallel clock-output signal
(PCLKO). PCLKO is the synthesized 2.488Gbps internal
serial-clock signal divided by 16. The allowable PCLKO
to PCLKI skew is 0ns to 4ns. This defines a timing win-
dow after the PCLKO rising edge, during which a PCLKI
rising edge may occur (Figure 1).
System Loopback
The MAX3891 is designed to provide system loopback
testing. The loopback outputs (SLBO) of the MAX3891
may be directly connected to the loopback inputs of a
deserializer (MAX3881) for system diagnostics. To
enable the SLBO outputs, apply a TTL logic-high signal
to the SOS input. The same signal that controls the SOS
enable input may also be used to control the SIS
enable input on the MAX3881.
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