MAX3885ECB-TD Maxim Integrated, MAX3885ECB-TD Datasheet - Page 6

• Manufacturer Part Number: MAX3885ECB-TD
• Description: Serializers & Deserializers - Serdes 3.3V 2.488Gbps SDH/ SONET 1
• Manufacturer: Maxim Integrated

Specifications of MAX3885ECB-TD

• Data Rate: 2.488 Gbps, 155 Mbps
• Number Of Inputs: 1
• Number Of Outputs: 16
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Maximum Operating Temperature: + 85 C
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Current: 200 mA
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

DC termination between the inverting and noninverting
outputs for proper operation. Do not terminate these
outputs to ground. The synchronization LVDS inputs
(SYNC+, SYNC-) are internally terminated with 100Ω
differential input resistance and, therefore, do not
require external termination.
Because of the self-biasing resistor networks, the serial
data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-)
require 53Ω termination to V
with a PECL source (see Alternative PECL Input
Termination ). This results in an equivalent input resis-
tance of 50Ω.
Figure 5 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
V
interfacing with an ECL-output device, the MAX3885’s
internal self-biasing allows easy ECL AC-coupling ter-
mination.
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3885 high-speed inputs and out-
puts.
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
Figure 4. Timing Parameters
6
CC
PD0–PD15
_______________________________________________________________________________________
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
- 2V termination voltage is not available. When
SCLK
PCLK
SD
Alternative PECL Input Termination
Applications Information
CC
Layout Techniques
- 2V when interfacing
PECL Inputs
t
SCLK
= 1 / f
t
CLK-Q
SCLK
Figure 5. Alternative PECL Input Termination
Z
Z
+3.3V
O
O
t
= 50Ω
= 50Ω
SU
Z
Z
O
O
= 50Ω
= 50Ω
THEVENIN-EQUIVALENT TERMINATION
ECL AC-COUPLING TERMINATION
133Ω
86.6Ω
t
133Ω
-2V
-2V
H
53Ω
53Ω
86.6Ω
PECL
INPUTS
PECL
INPUTS
MAX3885
MAX3885