MAX3885ECB-TD Maxim Integrated, MAX3885ECB-TD Datasheet - Page 4

• Manufacturer Part Number: MAX3885ECB-TD
• Description: Serializers & Deserializers - Serdes 3.3V 2.488Gbps SDH/ SONET 1
• Manufacturer: Maxim Integrated

Specifications of MAX3885ECB-TD

• Data Rate: 2.488 Gbps, 155 Mbps
• Number Of Inputs: 1
• Number Of Outputs: 16
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Maximum Operating Temperature: + 85 C
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Current: 200 mA
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
Figure 1. Driver Output Levels
4
1, 2, 8, 16, 17,
24, 32, 33, 41,
13, 25, 34, 42,
20, 22, 26, 28,
30, 35, 37, 39,
43, 45, 50, 52,
21, 23, 27, 29,
31, 36, 38, 40,
44, 46, 51, 53,
48, 49, 57, 64
54, 58, 60, 62
55, 59, 61, 63
3, 5, 7, 9, 11,
_______________________________________________________________________________________
47, 56
PIN
10
12
14
15
18
19
4
6
SINGLE-ENDED OUTPUT
DIFFERENTIAL OUTPUT
V
PD+
V
V
PD+
PD-
PD0+ to PD15+
PD0- to PD15-
- V
PD-
SYNC+
SCLK+
PCLK+
NAME
SCLK-
SYNC-
PCLK-
GND
SD+
V
SD-
CC
D
PD+
PD-
0V (DIFF.)
Ground
+3.3V Supply Voltage
Serial Data Noninverting PECL Input. Data is clocked on the SCLK signal’s positive transi-
tion.
Serial Data Inverting PECL Input. Data is clocked on the SCLK signal’s positive transition.
Serial Clock Noninverting PECL Input
Serial Clock Inverting PECL Input
Synchronizing Pulse Inverting LVDS Input. Pulse the SYNC signal high for at least four SCLK
periods to shift the data alignment by dropping one bit.
Synchronizing Pulse Noninverting LVDS Input. Pulse the SYNC signal high for at least four
SCLK periods to shift the data alignment by dropping one bit.
Parallel Clock Inverting LVDS Output
Parallel Clock Noninverting LVDS Output
Parallel Data Inverting LVDS Outputs. Data is updated on the negative transition of the PCLK
signal.
Parallel Data Noninverting LVDS Outputs. Data is updated on the negative transition of the
PCLK signal.
R
L
= 100Ω
|
V
OD
|
FUNCTION
V
V
0V
OD
+V
-V
OD
OD
Pin Description
V
OD, P - P
V
V
V
OS
OL
OH
= V
PD+
- V
PD-