MAX3880ECB-TD Maxim Integrated, MAX3880ECB-TD Datasheet - Page 6

• Manufacturer Part Number: MAX3880ECB-TD
• Description: Serializers & Deserializers - Serdes 3.3V 2.488Gbps SDH/ SONET 1
• Manufacturer: Maxim Integrated

Specifications of MAX3880ECB-TD

• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: TQFP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

The MAX3880 deserializer with clock recovery converts
2.488Gbps serial data to 16-bit-wide, 155Mbps parallel
data. The device combines a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
16-bit demultiplexer, clock divider, and LVDS output
buffer (Figure 3). The PLL consists of a phase/frequen-
cy detector (PFD), a loop filter, and a voltage-controlled
oscillator (VCO). The MAX3880 is designed to deliver
the best combination of jitter performance and power
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Figure 3. MAX3880 Functional Diagram
6
SYNC+
SYNC-
SLBI+
SLBI-
SDI+
SDI-
SIS
_______________________________________________________________________________________
V
V
CC
CC
50Ω
50Ω
100Ω
AMP
AMP
LVDS
Detailed Description
MUX
PHADJ+
TTL
FREQUENCY
DETECTOR
PHASE &
LOL
PHADJ-
FIL+
FILTER
MAX3880
LOOP
FIL-
dissipation by using a fully differential signal architec-
ture and low-noise design techniques. The PLL recov-
ers the serial clock from the serial input data stream.
The demultiplexer generates a 16-bit-wide 155Mbps
parallel data output.
The synchronization inputs (SYNC+, SYNC-) realign the
output data word. Realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. During synchronization, the first
incoming bit of data during that PCLK cycle is
VCO
D
CK
Q
DIVIDER
CLOCK
DEMULTIPLEXER
16-BIT
LVDS
LVDS
LVDS
LVDS
PD15+
PD15-
PD1+
PD1-
PCLK+
PCLK-
PD0+
PD0-