MAX3880ECB-TD Maxim Integrated, MAX3880ECB-TD Datasheet - Page 5

• Manufacturer Part Number: MAX3880ECB-TD
• Description: Serializers & Deserializers - Serdes 3.3V 2.488Gbps SDH/ SONET 1
• Manufacturer: Maxim Integrated

Specifications of MAX3880ECB-TD

• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: TQFP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

1, 17, 25, 33,
52, 54, 58, 60
53, 55, 59, 61
4, 7, 10, 13,
41, 49, 56,
24, 32, 40,
20, 22, 26,
28, 30, 34,
36, 38, 42,
44, 46, 50,
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
62, 64
48, 57
PIN
EP
11
12
14
15
16
18
19
63
2
3
5
6
8
9
Exposed Pad
PHADJ+
PD0+ to
PHADJ-
SYNC+
PD0- to
PCLK+
PD15+
NAME
SYNC-
PCLK-
SLBI+
PD15-
_______________________________________________________________________________________
SLBI-
GND
SDI+
FIL+
SDI-
V
LOL
FIL-
SIS
CC
1:16 Deserializer with Clock Recovery
Ground
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
+3.3V Supply Voltage
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
used.
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
used.
Positive Serial Data Input. 2.488Gbps data stream.
Negative Serial Data Input. 2.488Gbps data stream.
Positive System Loopback Input. 2.488Gbps data stream.
Negative System Loopback Input. 2.488Gbps data stream.
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
Negative Parallel Clock LVDS Output
Positive Parallel Clock LVDS Output
Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pull-up resistor). The
LOL monitor is valid only when a data stream is present on the inputs to the MAX3880.
Ground. This must be soldered to a circuit board for proper thermal performance (see Package
Information).
+3.3V, 2.488Gbps, SDH/SONET
FUNCTION
Pin Description
CC
CC
if not
if not
5