FT313HL-R FTDI, FT313HL-R Datasheet - Page 36

• Manufacturer Part Number: FT313HL-R
• Description: USB Interface IC USB High Speed USB Host Controller IC
• Manufacturer: FTDI

Specifications of FT313HL-R

• Rohs: yes
• Product: USB 2.0
• Data Rate: 480 Mbps
• Interface Type: USB
• Operating Supply Voltage: 1.62 V to 3.63 V
• Operating Supply Current: 35 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Minimum Operating Temperature: - 40 C

Bit
6
5
4
3
2
1
Name
OCINT
CLKREADY
BUSINACTIVE
REMOTEWKINT
DMAEOTINT
SOFINT
Copyright © 2012 Future Technology Devices International Limited
Type
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Default value
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
Description
disconnect
Indicates that wake up event is triggered.
The INT line will be asserted if the
respective enable bit in the HCINTEN
register is set.
0: No wake up event has occurred on the
port when device connects or disconnects.
1: Wake up event has occurred on the port
when device connects or disconnects.
Overcurrent interrupt
Indicates that overcurrent event is
triggered. The INT line will be asserted if
the respective enable bit in the HCINTEN
register is set.
0: No overcurrent event has occurred.
1: Overcurrent event has occurred.
Clock ready
Indicates that internal clock signals are
running stable. The INT line will be asserted
if the respective enable bit in the HCINTEN
register is set.
0: No clock ready event has occurred.
1: Clock ready event has occurred.
USB Bus inactive interrupt
Indicates that USB bus is inactive. The INT
line will be asserted if the respective enable
bit in the HCINTEN register is set.
0: USB bus is active.
1: USB bus is inactive.
Remote Wake up interrupt
Indicates INT was generated when the host
controller remote wakeup. The INT line will
be asserted if the respective enable bit in
the HCINTEN register is set.
0: No remote wake up.
1: Remote wake up event occurred.
DMA EOT interrupt
Indicates the DMA transfer completion. The
INT line will be asserted if the respective
enable bit in the HCINTEN register is set.
0: No DMA transfer is completed.
1: DMA transfer is completed.
SOF interrupt
The INT line will be asserted if the
respective bit enable is set.
Document No.: FT_000589
Clearance No.: FTDI# 318
36