MAX9258AGCM+ Maxim Integrated, MAX9258AGCM+ Datasheet - Page 26

• Manufacturer Part Number: MAX9258AGCM+
• Description: Serializers & Deserializers - Serdes Prog Serializer / Deserializer
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9258AGCM+

• Rohs: yes
• Data Rate: 840 Mbit/s
• Input Type: LVDS
• Output Type: LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 18
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Table 11. Format for 18-Bit Serial-Word Length with Parity (Parallel-Word Width = 14)
Table 12. Format for 16-Bit Serial-Word Length with Parity (Parallel-Word Width = 12)
Table 13. Format for 14-Bit Serial-Word Length with Parity (Parallel-Word Width = 10)
Serial LVDS data is transmitted least significant bit (LSB)
to most significant bit (MSB) as shown in
13. The ECU at startup can program the parallel word
width, serial frequency range, parity, spread-spec trum,
and pixel clock frequency range (see the
Register Table
The devices each have registers that can be configured
at startup. Depending on the word length, the MAX9257A
multiplies PCLK_IN (pixel clock) by 12, 14, 16, 18, or
20 using an internal PLL to gener ate the serial clock.
Use
quency and serial-data ranges. Parallel data is serialized
using the serial-clock and serialized bits are transmitted
at the MAX9257A LVDS outputs. The devices support
a wide range for PCLK_IN
frequency needs to change to a frequency outside the
pro grammed range, the ECU must program both the
MAX9257A and the MAX9258A in the same control chan-
nel session.
The word length and pixel clock is limited by the maxi-
mum serial-data rate of 840Mbps. The following formula
shows the relation between word length, pixel clock, and
serial clock:
For example, if PCLK_IN is 70MHz, the serial-word length
has to be 12 bits including DC balance bits if parity is not
enabled to keep the serial-data rate under 840Mbps. If
NAME
NAME
NAME
BIT
BIT
BIT
Serial-word length x pixel clock = serial-data rate =
Table 20
PR
PR
PR
1
1
1
for proper selection of available PCLK fre-
PRB
PRB
PRB
and the
2
2
2
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Fully Programmable Serializer/Deserializer
EN0
EN0
EN0
3
3
3
MAX9258A Register
840Mbps
Pixel Clock Frequency Range
EN1
EN1
EN1
(Table
4
4
4
Serial-Data Rate Range
HSYNC
HSYNC
HSYNC
LVDS Serial Data
14). If the pixel clock
5
5
5
Tables 5
VSYNC
VSYNC
VSYNC
Table).
6
6
6
MAX9257A
with UART/I
through
D0
7
D0
7
D0
7
D1
8
D1
8
Table 14. MAX9257A Pixel Clock Range
(PCLK�IN)
Table 15. Serial-Data Rate Range
the serial-word length is 20 bits, the maxi mum PCLK_IN
frequency is 42MHz. The serial-data rate can vary from
60Mbps to 840Mbps and can be programmed at power-
up
able PCLK frequency and serial data ranges. Operating
in the incorrect range for either the serial-data rate or
PCLK_IN can result in excessive current dissipation and
failure of the MAX9258A to lock to the MAX9257A.
The output common-mode bias is 1.2V at the LVDS
inputs on the MAX9258A and LVDS outputs on the
MAX9257A. No external resistors are required to provide
bias for AC-coupling the LVDS inputs and outputs.
D1
SERIAL-DATA RATE (Mbps)
8
D2
9
(Table
D2
FREQUENCY (MHz)
MAX9257A/MAX9258A
9
D3
10
D2
9
15). Use
100–200
200–400
400–840
60–100
D3
10
10–20
20–40
40–70
2
5–10
D4
11
C Control Channel
D3
10
D5
12
D4
11
Table 20
D6
13
LVDS Common-Mode Bias
D5
12
D4
11
for proper selection of avail-
D7
14
D6
13
PRATE (REG0[7:6])
SRATE (REG0[5:4])
D5
D8
12
15
D7
14
D9
16
00
01
10
11
00
01
10
11
D6
13
D8
D10
15
17
D7
14
D11
D9
16
18