MAX9240GTM+ Maxim Integrated, MAX9240GTM+ Datasheet - Page 39

• Manufacturer Part Number: MAX9240GTM+
• Description: Serializers & Deserializers - Serdes 28Bit GMSL Deserializer
• Manufacturer: Maxim Integrated

Specifications of MAX9240GTM+

• Rohs: yes

The deserializer checks the serial link for errors and
stores the number of detected and corrected errors
in the 8-bit registers, DETERR (0x10) and CORRERR
(0x12). If a large number of 8b/10b errors are detected
within a short duration (error rate R 1/4), the deserializer
loses lock and stops the error counter. The deserializer
then attempts to relock to the serial data. DETERR and
CORRERR reset upon successful video link lock, suc-
cessful readout of their respective registers (through FC),
or whenever autoerror reset is enabled. The deserializer
uses a separate PRBS register during the internal PRBS
test, and DETERR and CORRERR are reset to 0x00.
The deserializer has an open-drain ERR output. This
output asserts low whenever the number of detected/cor-
rected errors exceeds their respective error thresholds
during normal operation, or when at least one PRBS error
is detected during PRBS test. ERR reasserts high when-
ever DETERR and CORRERR reset, due to DETERR/
CORRERR readout, video link lock, or autoerror reset.
The default method to reset errors is to read the respec-
tive error registers in the deserializer (0x10, 0x12, and
0x13). Autoerror reset clears the error counters DETERR/
CORRERR and the ERR output ~1Fs after ERR goes low.
Autoerror reset is disabled on power-up. Enable autoer-
ror reset through AUTORST (0x08, D2). Autoerror reset
does not run when the device is in PRBS test mode.
Usually systems have one FC to run the control channel,
located on the serializer side for video-display appli-
cations or on the deserializer side for image-sensing
applications. However, a FC can reside on each side
simultaneously and trade off running the control channel.
In this case, each FC can communicate with the serializer
and deserializer and any peripheral devices.
Contention occurs if both FCs attempt to use the control
channel at the same time. It is up to the user to prevent
this contention by implementing a higher-level protocol.
Maxim Integrated
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Applications Information
Coax or STP Cable With Line Fault Detect
Autoerror Reset
Dual µC Control
Error Checking
ERR Output
In addition, the control channel does not provide arbitra-
tion between I
acknowledge frame is not generated when communica-
tion fails due to contention. If communication across the
serial link is not required, the FCs can disable the forward
and reverse control channel using the FWDCCEN and
REVCCEN bits (0x04, D[1:0]) in the serializer/deserial-
izer. Communication across the serial link is stopped and
contention between FCs cannot occur.
As an example of dual FC use in an image-sensing appli-
cation, the serializer can be in sleep mode and waiting
for wake-up by the FC on the deserializer side. After
wake-up, the serializer-side FC assumes master control
of the serializer’s registers.
It is recommended that the serial link be enabled after
the video clock (f
clock (f
frequency, stop the video clock for 5Fs, apply the clock
at the new frequency, then restart the serial link or toggle
SEREN. On-the-fly changes in clock frequency are pos-
sible if the new frequency is immediately stable and
without glitches. The reverse control channel remains
unavailable for 350Fs after serial link start or stop. When
using the UART interface, limit on-the-fly changes in
f
the device recognizes the UART sync pattern. For exam-
ple, when lowering the UART frequency from 1Mbps to
100kbps, first send data at 333kbps then at 100kbps for
reduction ratios of 3 and 3.333, respectively.
A measure of link quality is the recovery time from loss-
of-synchronization. The host can be quickly notified of
loss-of-lock by connecting the deserializer’s LOCK out-
put to the GPI input. If other sources use the GPI input,
such as a touch-screen controller, the FC can implement
a routine to distinguish between interrupts from loss-
of-sync and normal interrupts. Reverse control-channel
communication does not require an active forward link
to operate and accurately tracks the LOCK status of the
GMSL link. LOCK asserts for video link only and not for
the configuration link.
UART
to factors of less than 3.5 at a time to ensure that
UART
/f
I2C
2
C masters on both sides of the link. An
) are stable. When changing the clock
Changing the Clock Frequency
PCLKOUT
Loss-of-Synchronization
) and the control-channel
Fast Detection of
MAX9240
39