MAX9240GTM+ Maxim Integrated, MAX9240GTM+ Datasheet - Page 28

• Manufacturer Part Number: MAX9240GTM+
• Description: Serializers & Deserializers - Serdes 28Bit GMSL Deserializer
• Manufacturer: Maxim Integrated

Specifications of MAX9240GTM+

• Rohs: yes

The control channel is available for the FC to send and
receive control data over the serial link simultaneously
with the high-speed data. The FC controls the link from
either the serializer or the deserializer side to support
video-display or image-sensing applications. The control
channel between the FC and serializer or deserializer
runs in base mode or bypass mode, according to the
mode selection (MS/HVEN) input of the device connect-
ed to the FC. Base mode is a half-duplex control channel
and bypass mode is a full-duplex control channel.
In base mode, the FC is the host and can access the
registers of both the serializer and deserializer from
either side of the link using the GMSL UART protocol.
The FC can also program the peripherals on the remote
side by sending the UART packets to the serializer or
deserializer, with the UART packets converted to I
by the device on the remote side of the link. The FC
communicates with a UART peripheral in base mode
(through INTTYPE register settings), using the half-
duplex default GMSL UART protocol of the serial-
izer/deserializer. The device addresses of the serializer/
deserializer in base mode are programmable. The
default value is 0x80 for the serializer and is determined
by the CX/TP input for the deserializer
When the peripheral interface is I
deserializer convert UART packets to I
device addresses different from those of the serializer or
deserializer. The converted I
original UART bit rate.
Figure 16. GMSL UART Protocol for Base Mode
Maxim Integrated
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
SYNC
SYNC
Coax or STP Cable With Line Fault Detect
Register Programming
2
DEV ADDR + R/W
DEV ADDR + R/W
C bit rate is the same as the
Control Channel and
UART Interface
2
MASTER WRITES TO SLAVE
C, the serializer/
(Table
REG ADDR
REG ADDR
2
C that have
8).
MASTER WRITES TO SLAVE
NUMBER OF BYTES
NUMBER OF BYTES
READ DATA FORMAT
WRITE DATA FORMAT
2
C
The deserializer uses differential line coding to send
signals over the reverse channel to the serializer. The
bit rate of the control channel is 9.6kbps to 1Mbps in
both directions. The serializer/deserializer automatically
detect the control-channel bit rate in base mode. Packet
bit-rate changes can be made in steps of up to 3.5
times higher or lower than the previous bit rate. See the
Changing the Clock Frequency
tion on changing the control-channel bit rate.
Figure 16
ing in base mode between the FC and the serializer/
deserializer.
Figure 17
Figure 19
and the ACK byte (0xC3). The FC and the connected
slave chip generate the SYNC byte and ACK byte,
respectively. Events such as device wake-up and GPI
generate transitions on the control channel that can be
ignored by the FC. Data written to the serializer/deserial-
izer registers do not take effect until after the ACK byte
is sent. This allows the FC to verify that write commands
are received without error, even if the result of the write
command directly affects the serial link. The slave uses
the SYNC byte to synchronize with the host UART’s data
rate. If the GPI or MS/HVEN inputs of the deserializer
toggle while there is control-channel communication, or if
a line fault occurs, the control-channel communication is
corrupted. In the event of a missed or delayed acknowl-
edge (~1ms due to control-channel timeout), the FC
should assume there was an error in the packet when the
slave device received it, or that an error occurred during
the response from the slave device. In base mode, the
FC must keep the UART Tx/Rx lines high for 16 bit times
before starting to send a new packet.
MASTER READS FROM SLAVE
BYTE 1
ACK
shows the UART protocol for writing and read-
shows the UART data format.
detail the formats of the SYNC byte (0x79)
BYTE 1
BYTE N
MASTER READS FROM SLAVE
BYTE N
section for more informa-
ACK
MAX9240
Figure 18
and
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