PCAL9555AHF,128 NXP Semiconductors, PCAL9555AHF,128 Datasheet - Page 16

• Manufacturer Part Number: PCAL9555AHF,128
• Description: Interface - I/O Expanders
• Manufacturer: NXP Semiconductors

Specifications of PCAL9555AHF,128

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HWQFN-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders

NXP Semiconductors
PCAL9555A
Product data sheet
Fig 9.
SDA
(cont.)
Remark: Transfer can be stopped at any time by a STOP condition.
Read from register
S
START condition
S
(repeated)
START condition
0
7.2 Reading the port registers
0
1
slave address
1
0
slave address
0
In order to read data from the PCAL9555A, the bus master must first send the
PCAL9555A address with the least significant bit set to a logic 0 (see
“PCAL9555A device
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte is sent by the PCAL9555A (see
Figure
pulse. After the first byte is read, additional bytes may be read but the data now reflects
the information in the other register in the pair. For example, if Input Port 1 is read, the
next byte read is Input Port 0. There is no limit on the number of data bytes received in
one read transmission, but on the final byte received the bus master must not
acknowledge the data.
After a subsequent restart, the command byte contains the value of the next register to be
read in the pair. For example, if Input Port 1 was read last before the restart, the register
that is read after the restart is the Input Port 0.
0 A2 A1 A0
0 A2 A1 A0 1
acknowledge
11). Data is clocked into the register on the falling edge of the acknowledge clock
acknowledge
from slave
R/W
from slave
0
R/W
A
All information provided in this document is subject to legal disclaimers.
A
0
Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up
MSB
0/1 0
address”). The command byte is sent after the address and
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
Rev. 1 — 3 October 2012
upper byte of register
command byte
data from lower or
DATA (first byte)
0 0/1 0/1 0/1 0/1
acknowledge
from slave
LSB
A
A
acknowledge
from master
(cont.)
MSB
lower byte of register
data from upper or
DATA (last byte)
no acknowledge
Figure
PCAL9555A
from master
LSB
9,
Figure 4
© NXP B.V. 2012. All rights reserved.
Figure 10
NA
002aah374
P
STOP
condition
and
16 of 46