73S8010C-IMR/F1 Maxim Integrated, 73S8010C-IMR/F1 Datasheet - Page 14

• Manufacturer Part Number: 73S8010C-IMR/F1
• Description: I2C Interface IC
• Manufacturer: Maxim Integrated

Specifications of 73S8010C-IMR/F1

• Rohs: yes

A power-on-reset (POR) event will reset all of the control and status registers to their default states. A V
event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that
creates interval “t
considered valid for V
11 Warm Reset
The 73S8010C automatically asserts a warm reset to the card when instructed through bit 1 of the I
register (Warm Reset bit). The warm reset length is automatically defined as 42,000 card clock cycles. The bit
Warm Reset is automatically reset when the card starts answering or when the card is declared mute.
12 I/O Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are high when the
activation sequencer turns on the I/O reception state. See
details on when the I/O reception is enabled.
The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset. When the control I/O enable
bit (bit 7 of the Control register) is set, the first I/O line on which a falling edge is detected becomes the
input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected
then both I/O lines return to their neutral state. The delay between the I/O signals is shown in
14
Warm Reset
Delay from I/O to I/OUC:
Delay from I/OUC to I/O:
(bit 1)
RST
t
t
t
IO
1
2
3
> 1.5 µs, Warm Reset Starts
= 42000 card clock cycles, End of Warm Reset
= Resets Warm Reset bit 1 when detected ATR or Mute
1
,” will not clear the interrupt until V
DD
as low as 1.5 to 1.8 volts. At the lower range of the V
t
1
t
t
Figure 9: Warm Reset operation
IO_HL
I/OUC_HL
= 100 ns
Figure 10: I/O Timing
= 100 ns
DD
is valid for at least the t
t
2
t
t
IO_LH
I/OUC_LH
Section 8 Activation Sequence
= 25 ns
= 25 ns
1
DD
time. The V
fault, POR will be asserted.
t
3
DD
fault can be
for more
Figure
2
C Control
Rev. 1.5
DD
10.
fault