CAT25256ZD2I-GT2 ON Semiconductor, CAT25256ZD2I-GT2 Datasheet - Page 9

• Manufacturer Part Number: CAT25256ZD2I-GT2
• Description: EEPROM 256KB SPI SER CMOS EEPROM
• Manufacturer: ON Semiconductor

Specifications of CAT25256ZD2I-GT2

• Rohs: yes
• Memory Size: 256 Kbit
• Organization: 32 x 8
• Data Retention: 100 yr
• Maximum Clock Frequency: 1000 KHz
• Maximum Operating Current: 2 mA
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TDFN-8
• Interface Type: SPI
• Minimum Operating Temperature: - 40 C

Byte Write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 15 significant address
bits are used by the CAT25256. The 16th address bit is don’t
care, as shown in Table 14. Internal programming will start
after the low to high CS transition. During an internal write
cycle, all commands, except for RDSR (Read Status
Register) will be ignored. The RDY bit will indicate if the
internal write cycle is in progress (RDY high), or the device
is ready to accept commands (RDY low).
Page Write
may continue sending data, up to a total of 64 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT25256 is
*New Product only.
Table 14. BYTE ADDRESS
Main Memory Array
Identification Page*
Once the WEL bit is set, the user may execute a write
After sending the first data byte to the CAT25256, the host
SCK
SCK
SO
CS
SO
CS
SI
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
0
0
0
0
0
0
1
1
0
0
2
HIGH IMPEDANCE
2
0
0
3
3
OPCODE
OPCODE
0
0
4
4
Address Significant Bits
0
0
5
5
1
1
6
A14 − A0
6
A5 − A0
0
0
Figure 6. Page WRITE Timing
Figure 5. Byte WRITE Timing
7
7
A
A
N
N
8
8
BYTE ADDRESS*
BYTE ADDRESS*
http://onsemi.com
HIGH IMPEDANCE
21 22 23 24 25 26 27
21 22 23 24−31 32−39
9
automatically returned to the write disable state. While the
internal write cycle is in progress, the RDSR command will
output the RDY (Ready) bit status only (i.e., data out = FFh).
Write Identification Page
written with user data using the same Write commands
sequence as used for Page Write to the main memory array
(Figure 6). The IPL bit from the Status Register must be set
(IPL = 1) using the WRSR instruction, before attempting
to write to the IP.
[A5:A0] bits define the byte address within the
Identification Page. In addition, the Byte Address must point
to a location outside the protected area defined by the BP1,
BP0 bits from the Status Register. When the full memory
array is write protected (BP1, BP0 = 1,1), the write
instruction to the IP is not accepted and not executed.
the Status Register is set to 1 (the page is locked in
Read−only mode).
Address Don’t Care Bits
A
A
The additional 64−byte Identification Page (IP) can be
The address bits [A15:A6] are Don’t Care and the
Also, the write to the IP is not accepted if the LIP bit from
0
0
Byte 1
D7 D6 D5 D4 D3 D2 D1 D0
Data
* Please check the Byte Address Table (Table 14)
* Please check the Byte Address Table (Table 14)
A15 − A6
A15
Byte 2
Data
DATA IN
Byte 3
DATA IN
Data
24+(N−1)x8−1 .. 24+(N−1)x8
28
Data Byte N
7..1
29 30 31
# Address Clock Pulses
0
24+Nx8−1
16
16