GTL2002D,112 NXP Semiconductors, GTL2002D,112 Datasheet - Page 6

• Manufacturer Part Number: GTL2002D,112
• Description: IC XLATR 2BIT BI-DIREC 8SOIC
• Manufacturer: NXP Semiconductors

Specifications of GTL2002D,112

• Logic Function: Translator, Bidirectional
• Number Of Bits: 2
• Input Type: Voltage
• Output Type: Voltage
• Number Of Channels: 2
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 1.5ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Supply Voltage: 3 V ~ 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Other names: 568-4224-5; 935268311112; GTL2002D; GTL2002D

NXP Semiconductors
GTL2002_7
Product data sheet
8.2 Unidirectional down translation
8.3 Unidirectional up translation
For unidirectional clamping, higher voltage to lower voltage, the GREF input must be
connected to DREF and both pins pulled to the higher side V
(typically 200 k ). A filter capacitor on DREF is recommended. Pull-up resistors are
required if the chip set I/O are open-drain. The opposite side of the reference transistor
(SREF) is connected to the processor core supply voltage. When DREF is connected
through a 200 k resistor to a 3.3 V to 5.5 V V
to (V
For unidirectional up translation, lower voltage to higher voltage, the reference transistor is
connected the same as for a down translation. A pull-up resistor is required on the higher
voltage side (Dn or Sn) to get the full HIGH level, since the GTL-TVC device will only pass
the reference source (SREF) voltage as a HIGH when doing an up translation. The driver
on the lower voltage side only needs pull-up resistors if it is open-drain.
Fig 7.
Fig 8.
CC
easy migration to lower voltage
as processor geometry shrinks
easy migration to lower voltage
as processor geometry shrinks
Typical unidirectional HIGH-to-LOW voltage translation.
Unidirectional down translation to protect low voltage processor pins
Typical unidirectional LOW-to-HIGH voltage translation.
Unidirectional up translation to higher voltage chip sets
1.5 V), the output of each Sn has a maximum output voltage equal to SREF.
1.8 V
1.5 V
1.2 V
1.0 V
1.8 V
1.5 V
1.2 V
1.0 V
V
V
totem pole I/O
or open-drain
CORE
CORE
CPU I/O
CPU I/O
Rev. 07 — 2 July 2009
GND
SREF
S1
S2
GND
SREF
S1
S2
CC
2-bit bidirectional low voltage translator
GREF
GREF
DREF
DREF
supply and SREF is set between 1.0 V
D1
D2
D1
D2
200 k
200 k
CC
through a pull-up resistor
GTL2002
© NXP B.V. 2009. All rights reserved.
totem pole I/O
CHIPSET I/O
CHIPSET I/O
002aac061
002aac062
V
V
CC
CC
5 V
5 V
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