MAX1267ACEG+T Maxim Integrated, MAX1267ACEG+T Datasheet - Page 8

• Manufacturer Part Number: MAX1267ACEG+T
• Description: Analog to Digital Converters - ADC 12-Bit 2Ch 265ksps 3.6V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1267ACEG+T

• Rohs: yes
• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 265 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 70 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
________________Detailed Description
The MAX1265/MAX1267 ADCs use a successive-
approximation (SAR) conversion technique and an input
track/hold (T/H) stage to convert an analog input signal
to a 12-bit digital output. This output format provides an
easy interface to standard microprocessors (µPs). Figure
2 shows the simplified internal architecture of the
MAX1265/MAX1267.
8
Figure 2. Simplified Functional Diagram of 6-/2-Channel MAX1265/MAX1267
MAX1265
_______________________________________________________________________________________
25
26
27
28
(CH5)
(CH4)
(CH3)
(CH2)
COM
CH1
CH0
CLK
WR
INT
CS
RD
PIN
MAX1267
( ) ARE FOR MAX1265 ONLY.
21
22
23
24
CLOCK
MULTIPLEXER
ANALOG
INPUT
NAME
Converter Operation
V
REF
D11
D10
DD
CONTROL LOGIC
LATCHES
AND
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor
to GND when using the internal reference.
Analog +2.7V to +3.6V Power Supply. Bypass with a 0.1µF capacitor to GND.
Tri-State Digital Output (D11)
Tri-State Digital Output (D10)
REF
T/H
12
CHARGE REDISTRIBUTION
TRI-STATE, BIDIRECTIONAL
12-BIT DAC
I/O INTERFACE
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1265
(Figure 3a) and to CH0–CH1 for the MAX1267 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
APPROXIMATION
SUCCESSIVE-
REGISTER
12-BIT DATA BUS
12
D0–D11
A
2.05
V
FUNCTION
Pin Description (continued)
=
MAX1265
MAX1267
REFADJ
Pseudo-Differential Operation
COMP
17kΩ
REFERENCE
1.22V
Single-Ended and
V
GND
DD