MAX1267ACEG+T Maxim Integrated, MAX1267ACEG+T Datasheet - Page 12

• Manufacturer Part Number: MAX1267ACEG+T
• Description: Analog to Digital Converters - ADC 12-Bit 2Ch 265ksps 3.6V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1267ACEG+T

• Rohs: yes
• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 265 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 70 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
and start of conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0 (all other bits in
control byte unchanged), terminates acquisition and
starts conversion on WR rising edge (Figure 5).
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
A standard interrupt signal, INT, is provided to allow the
MAX1265/MAX1267 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
12
Figure 5. Conversion Timing Using External Acquisition Mode
______________________________________________________________________________________
CS
D11–D0
INT
DOUT
WR
RD
t
CSWS
HIGH-Z
t
DS
ACQMOD = 1
t
t
CS
WR
CONTROL
Reading a Conversion
BYTE
External Acquisition
t
t
CSWH
DH
t
ACQ
ACQMOD = 0
CONTROL
BYTE
t
CONV
when the conversion is complete and the output data is
ready (Figures 4 and 5). It returns high on the first read
cycle or if a new control byte is written.
The MAX1265/MAX1267 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The part retains
the last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock mode, internal or external acquisition
can be used. At power-up, the MAX1265/MAX1267
enter the default external clock mode.
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. Bit D7 of
the control byte must be set to 1 and bit D6 must be set
to zero. The internal clock frequency is then selected,
resulting in a conversion time of 3.6µs. When using the
internal clock mode, tie the CLK pin either high or low
to prevent the pin from floating.
t
D0
t
INT1
VALID DATA
Selecting Clock Mode
t
Internal Clock Mode
TR
HIGH-Z