MAX1068ACEG+T Maxim Integrated, MAX1068ACEG+T Datasheet - Page 14

• Manufacturer Part Number: MAX1068ACEG+T
• Description: Analog to Digital Converters - ADC MultiCh 14-Bit 200ksps
• Manufacturer: Maxim Integrated

Specifications of MAX1068ACEG+T

• Rohs: yes
• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The MAX1067/MAX1068 feature an SPI/QSPI/
MICROWIRE-compatible 3-wire serial interface. The
MAX1067 digital interface consists of digital inputs CS,
SCLK, and DIN; and outputs DOUT and EOC. The
MAX1067 operates in the following modes:
• SPI interface with external clock
• SPI interface with internal clock
• SPI interface with internal clock and scan mode
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
Figure 5. MAX1067 Typical Operating Circuit
Figure 7. Equivalent Input Circuit
Table 1. Command/Configuration/Control Register
14
COMMAND
AIN_
POWER-UP
ANALOG
INPUTS
STATE
+5V
+5V
______________________________________________________________________________________
DIN
R
DSON
C
MUX
MUX
BIT7 (MSB)
CH SEL2
1µF
TRACK
HOLD
C
0.1µF
SWITCH
0.1µF
0
REF
DV
REF
AV
AIN0
AIN1
AIN2
AIN3
DIN
CAPACITIVE
CH SEL1
AGND
DD
DD
C
HOLD
DAC
DAC
BIT6
Digital Interface
0
MAX1067
GND
TRACK
R
CH SEL0
REFCAP
IN
ZERO
DGND
AGND
AGND
SCLK
DOUT
BIT5
EOC
CS
0
AUTO-ZERO
RAIL
CS
SCLK
DOUT
EOC
0.1µF
SCAN1
BIT4
0
SCAN0
BIT3
In addition to the standard 3-wire serial interface modes,
the MAX1068 includes a DSPR input and a DSPX output
for communicating with DSPs in external clock mode
and a DSEL input to determine 8-bit-wide or 16-bit-wide
data-transfer mode. When not using the MAX1068 in the
DSP interface mode, connect DSPR to DV
DSPX unconnected.
Table 1 shows the contents of the command/configura-
tion/control register and the state of each bit after initial
power-up. Tables 2–6 define the control and configura-
tion of the device for each bit. Cycling the power sup-
plies resets the command/configuration/control register
to the power-on-reset default state.
A logic high on CS places the MAX1067/MAX1068 in the
shutdown mode chosen by the power-down bits, and
places DOUT in a high-impedance state. Drive CS low to
power-up and enable the MAX1067/MAX1068 before
starting a conversion. In internal reference mode, allow
5ms for the shutdown internal reference and/or buffer to
wake and stabilize before starting a conversion. In exter-
nal reference mode (or if the internal reference is already
on), no reference settling time is needed after power-up.
Figure 6. MAX1068 Typical Operating Circuit
0
Command/Configuration/Control Register
ANALOG
INPUTS
8
+5V
+5V
DIN
REF/PD_SEL1
16
BIT2
1
1µF
0.1µF
0.1µF
Initialization After Power-Up
REF/PD SEL0
DV
DSPR
REF
AV
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
DIN
DSEL
DD
DD
BIT1
MAX1068
1
GND
REFCAP
DGND
DOUT
AGND
AGND
SCLK
DSPX
EOC
CS
INT/EXT CLK
DD
BIT0 (LSB)
DOUT
CS
SCLK
DSPX
EOC
0.1µF
and leave
0