ZADCS0822IS14T ZMDI, ZADCS0822IS14T Datasheet - Page 21

• Manufacturer Part Number: ZADCS0822IS14T
• Description: Analog to Digital Converters - ADC ADC
• Manufacturer: ZMDI

Specifications of ZADCS0822IS14T

• Product Category: Analog to Digital Converters - ADC
• Rohs: yes
• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Differential
• Snr: 49 dB
• Interface Type: Microwire, QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-14
• Maximum Power Dissipation: 250 mW
• Minimum Operating Temperature: - 25 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

Field Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC) may use this
operation mode.
Digital Timing
In general the clock frequency at SCLK may vary from 0.1MHz to 3.3MHz. Considering all telegram pauses or
other interruptions of a continuous clock at SCLK, each conversion must be completed within 1.2ms from the
falling clock edge of the eighth bit in the Control Byte. Otherwise the signal that was captured during
sample/hold may drop to noticeable affect the conversion result. Further detailed timing information on the
digital interface is provided in Table 8 and Figure 15.
Parameter
SCLK Periode
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
nCS Fall to SCLK Setup
SCLK Fall to
DOUT & SSTRB Hold
SCLK Fall to
DOUT & SSTRB Valid
nCS Rise to
DOUT & SSTRB Disable
nCS Fall to
DOUT & SSTRB Enable
nCS Pulse Width High
Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V;
Figure 15 Detailed Timing Diagram
Data Sheet
October 12, 2011
SSTRB
DOUT
ZADCS0882/0842/0822
8-Bit, 300ksps, ADC Family
SCLK
nCS
DIN
t
nCSSetup
t
t
OutEnable
OutEnable
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
t
DINsetup
t
SCLKhigh
t
SCL
Symbol Conditions
t
t
t
t
t
t
t
t
t
t
t
SCLK
SCLKhigh
SCLKlow
DinSetup
DinHold
nCSSetup
OutHold
OutValid
OutDisable
OutEnable
nCSHigh
t
DINhold
t
C
C
C
C
SCLKlow
Load
Load
Load
Load
t
nCSHig
= 20pF
= 20pF
= 20pF
= 20pF

OP
=

OPmin
…

OPmax
t
OutValid
)
303.0
151.5
151.5
Min
100
30
10
30
10
10
t
OutHold
Typ
Max
40
60
60
21 of 26
t
OutDisable
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns