ZADCS0822IS14T ZMDI, ZADCS0822IS14T Datasheet - Page 19

• Manufacturer Part Number: ZADCS0822IS14T
• Description: Analog to Digital Converters - ADC ADC
• Manufacturer: ZMDI

Specifications of ZADCS0822IS14T

• Product Category: Analog to Digital Converters - ADC
• Rohs: yes
• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Differential
• Snr: 49 dB
• Interface Type: Microwire, QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-14
• Maximum Power Dissipation: 250 mW
• Minimum Operating Temperature: - 25 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

Figure 11: 24-Clock External Clock Mode Timing (f
Figure 12: Internal Clock Mode Timing with interleaved Control Byte transmission
Table 7 Control Byte Format
Data Sheet
October 12, 2011
BIT
7
(MSB)
6
5
4
3
2
1
0 (LSB)
ZADCS0882/0842/0822
8-Bit, 300ksps, ADC Family
SSTRB
SSTRB
DOUT
SCLK
DOUT
SCLK
nCS
DIN
nCS
DIN
Name
START
A2
A1
A0
UNI/BIP
SGL/DIF
PD1
PD0
(Start)
(Start)
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
S
S
1
1
A2
A2
Idle
Idle
Description
The Start Bit is defined by the first logic ‘1’ after nCS goes low.
Channel Select Bits. Along with SGL/DIF these bits control the setting of the input multiplexer.
For further details on the decoding see also Table 5 and Table 6.
Output Code Bit. The value of the bit determines conversion mode and output code format.
‘1’
‘0’
Single-Ended / Differential Select Bit. Along with the Channel Select Bits A2 .. A0 this bit
controls the setting of the input multiplexer
‘1’
‘0’
Power Down and Clock Mode Select Bits
PD1
A1
0
0
1
1
A1
A0
A0
UNI/
BIP
UNI/
BIP
=
=
=
=
PD0
SGL/
0
1
0
1
DIF
SGL/
DIF
Acquire
PD1 PD0
Acquire
PD1 PD0
t
ACQ
unipolar - straight binary coding
bipolar - two’s complement coding
single ended - all channels CH0 … CH7 measured referenced to COM
differential - the voltage between two channels is measured
Mode
Full Power-Down
Fast Power-Down
Internal clock mode
External clock mode
8
8
Conversion
1
t
(MSB)
CONV
B7
B6
SCLK
B5
1
≤ 3.3MHz)
(MSB)
Conversion
B4
B7
B3
B6
B2
B5
B1
B4
8
(LSB)
B3
Result Output
B0
1
B2
B1
8
(LSB)
B0
S
1
A2
A1
Zero filled
A0
Idle
UNI/
BIP
8
SGL/
DIF
Zero filled
Acquire
PD1 PD0
8
19 of 26