P2041NXE1PNB Freescale Semiconductor, P2041NXE1PNB Datasheet - Page 2

• Manufacturer Part Number: P2041NXE1PNB
• Description: Digital Signal Processors & Controllers - DSP, DSC P2041-1500MHZ EXT TEMP
• Manufacturer: Freescale Semiconductor

Specifications of P2041NXE1PNB

• Rohs: yes

Features
Four e500mc cores, built on Power
Architecture technology
• 4x e500mc cores (P2040: up to 1.2 GHz;
• 32 KB L1-I cache and 32 KB L1-D
• 128 KB L2 cache per core (P2041 only)
Memory controller
• DDR3/3L up to 1.2 GHz (P2040) and
• 32/64-bit data bus w/ECC
High-speed interconnects
• 10 x 5 GHz SerDes lanes
• 3 x PCI Express 2.0 controllers
• 2 x Serial RapidIO 1.3/2.1 controllers
• 2 x SATA 2.0 at 3 Gbps
CoreNet Switch Fabric
• 1 MB CoreNet platform cache with ECC
• Peripheral access management unit (PAMU)
QorIQ P2040/P2041 Communication Processors
P2041: up to 1.5 GHz)
cache per core
1.33 GHz (P2041)
controls external device access to
memory space
Security Fuse Processor
Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)
Accelerators and Memory Control
2x USB 2.0 with PHY
Security Monitor
16-bit eLBC
2x DUART
SPI, GPIO
SD/MMC
Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet
is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective
owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are
trademarks and service marks licensed by Power.org. © 2011 Freescale Semiconductor, Inc.
Document Number: QP2040FS
REV 2
eSDHC
4x I
2
C
RapidIO
Serial
(P2041 only)
Mgr.
L2 Cache
Backside
128 KB
®
Security
Pattern
Engine
Match
4.2
2.1
PAMU
Networking Elements
Queue
Buffer
Ethernet
• 10 GE/XAUI (P2041 only)
• Up to 5x SGMII, 4x 2.5 Gbps SGMII, 2x
• All with classification, hardware queueing,
Data path acceleration
• SEC 4.2: Public key accelerator, DES,
• PME 2.1: Searches for 128 byte text strings
• RapidIO messaging: Type 9 and 11
Additional peripheral interfaces
• SD/MMC
• SPI controller
• Four I
• 2x USB 2.0 with PHY
• Two dual UARTs
• Enhanced local bus controller (eLBC), 16-bit
Mgr.
Mgr.
D-Cache
RGMII
policing, buffer management, checksum
offload, QoS, lossless flow control, IEEE
AES, message digest accelerator, random
number generator, ARC4, SNOW 3G F8 and
F9, CRC, Kasumi
in 32 KB patterns in 128 million sessions
32 KB
Power Architecture
2
e500mc Core
(P2041
C controllers
10 GE
Parse, Classify,
only)
Frame Manager
Distribute
PAMU
1GE 1GE
1GE 1GE
Basic Peripherals and Interconnect
1GE
I-Cache
32 KB
CoreNet Coherency Fabric
®
SATA
PAMU
2.0
Learn More:
SATA
2.0
10-Lane 5 GHz SerDes
®
1588
Frontside CoreNet
Platform Cache
PCIe PCIe
DMA
1024 KB
Device
• 45 nm SOI process technology
• 783-pin FCPBGA package, 23 mm x 23 mm
Enablement
• Enea
• Green Hills
• Mentor Graphics
• CodeSourcery: GCC and GDB tool chain
• P2040RDB and P2041RDB reference
For current information about Freescale
products and documentation, please visit
freescale.com/QorIQ.
and hardware development tools, trace
tools and real-time operating systems
Linux
design boards
PAMU
PCIe
®
®
: Real-time operating system support
solution
Peripheral Access
Management Unit
®
SRIO SRIO
: Complete portfolio of software
DMA
®
: Commercial grade
Memory Controller
DDR3/3L
64-bit
Real-Time Debug
Monitor
Perf.
Watchpoint
Trigger
Aurora
Cross
CoreNet
Trace