P2041NXE1PNB Freescale Semiconductor, P2041NXE1PNB Datasheet

P2041NXE1PNB

Manufacturer Part Number

P2041NXE1PNB

Description

Digital Signal Processors & Controllers - DSP, DSC P2041-1500MHZ EXT TEMP

Manufacturer

Freescale Semiconductor

Datasheet

1.P2041NXE1PNB.pdf (2 pages)

Specifications of P2041NXE1PNB

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QorIQ Communications Platforms

P2 Series

P2040 and P2041 low-end and mid-range quad-core processors

Overview

The QorIQ P2040 (to 1.2 GHz) and higher

performance pin-compatible P2041 (to 1.5

GHz) quad-core processors, built on Power

Architecture

architectural features pioneered in the P4

platform into the low-end (P2040) and mid-

range (P2041) quad core space. This helps to

enable customers to scale software up and

down the QorIQ product line.

The architectural commonalities with other

QorIQ products include the e500mc core,

hardware hypervisor for robust virtualization

support, data path acceleration architecture

(DPAA) for offloading packet handling tasks

from the core, and the CoreNet switch fabric

which eliminates internal bottlenecks.

The architectural similarities are

complemented by a DPAA application

programming interface (API) such that all

devices with DPAA are programmed in the

same manner. Additionally, all DPAA devices

are supported with common GUI-based

configuration tools and use-case applications,

which are simple applications that establish

the basic infrastructure of programming the

DPAA. Developers can build applications on

top of these. With these tools, code written

for other DPAA-enabled devices can easily be

developed and ported to the P2040 processor.

The P2040 and P2041 processors are pin

compatible, sharing a 23 x 23 mm package.

The P2041 is a superset of the P2040. The

unique characteristics of each device are

outlined below.

Additional features supported by both devices

include up the three PCI Express

Serial RapidIO

USB interfaces.

Features

Frequency

Range

Cache

Hierarchy

Ethernet

Connectivity

technology, bring high-end

P2040

667–1200 MHz

32 KB I/D + 1 MB

CoreNet Platform

Cache

5x Gigabit

Ethernet

ports, two SATA ports and two

P2041

1200–1500 MHz

32 KB I/D + 128 KB

L2/core + 1 MB

CoreNet Platform

Cache

5x Gigabit Ethernet

+ XAUI (10 GE)

ports, two

Key Architectural Features

• Hardware hypervisor: The e500mc core

• DPAA: This is a set of blocks that together

• CoreNet switch fabric: The fabric-based

supports a hardware hypervisor that is

designed to enable each core to run its own

operating system completely independent

of the other core. The hypervisor facilitates

resource sharing and partitioning in a

multicore environment and provides

protection in the event that a core, driven

by malicious or improperly programmed

code, tries to access memory does not have

permission to read or write. It also allows the

sharing and partitioning of various I/Os across

the cores and helps ensure that incoming

memory mapped transactions are written only

into appropriate ranges of the memory map.

The DPAA achieves near-linear scaling as

additional cores are applied to a task.

offload basic work from the cores, allowing

the cores to perform higher value tasks or

to achieve application performance targets

at lower frequency, cost and power.

The DPAA consists of:

interface provides scalable on-chip, point-

to-point connectivity supporting concurrent

traffic to and from multiple resources

Frame manager, which implements

policing, classification and scheduling

over Ethernet ports

Queue manager, which performs queuing,

congestion control and workload

distribution and packet ordering

Buffer manager, which assigns packets

to right-sized buffers to minimize memory

consumption

Security block, for implementing crypto

algorithms

RapidIO message manager, which allows

Type9 and Type11 packets to connect

directly with DPAA infrastructure

Pattern matching engine, to search for

text strings in packets for unified threat

management

• Secure Boot: This feature ensures that the

Target Applications

The P2040 and P2041 processors are targeted

at mixed control plane and data plane

applications, where in previous generations,

separate devices would implement each

function. Typically, one or two cores would

implement the control plane, while the remaining

cores implement the data plane. The hardware

hypervisor facilitates this, with its capability to

safely provision flexible core allocations into

groups running SMP, one core running alone,

separate cores running in parallel or a core

running end-user applications.

With over a 2x performance range in a single

package, the P2040 and P2041 processors

together allow customers to use bill of materials

(BOM) stuffing options in a single board

to develop a range of products at different

performance and price points. For instance, the

P2040 processor addresses the fixed router and

the P2041 processor the modular router. The

P2040 may address the LTE channel card while

the P2041 the NIC. Other applications include

UTM, aerospace and defense, multi-function

printers and factory automation.

connected to the fabric, eliminating single-

point bottlenecks for non-competing

resources. This is designed to eliminate bus

contention and latency issues associated

with scaling shared bus architectures that

are common in other multicore approaches.

P2040 and P2041 processors only run

authenticated code. Through a set of fuses

that OEMs can program once but can never

be read, Secure Boot prevents unauthorized

parties from reverse engineering code to steal

intellectual property, from loading illegitimate

code to change system functionality or from

extracting sensitive user information that may

be stored in the system.

Related parts for P2041NXE1PNB

P2041NXE1PNB Summary of contents

Page 1

QorIQ Communications Platforms P2 Series P2040 and P2041 low-end and mid-range quad-core processors Overview The QorIQ P2040 (to 1.2 GHz) and higher performance pin-compatible P2041 (to 1.5 GHz) quad-core processors, built on Power Architecture technology, bring high-end ® architectural features ...

Page 2

... Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © ...

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