dsPIC33FJ06GS001-I/SO Microchip Technology, dsPIC33FJ06GS001-I/SO Datasheet - Page 6
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dsPIC33FJ06GS001-I/SO
Manufacturer Part Number
dsPIC33FJ06GS001-I/SO
Description
Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 6 KB FL 256Bytes RAM SMPS
Manufacturer
Microchip Technology
Datasheet
1.DSPIC33FJ09GS302-ISP.pdf
(52 pages)
Specifications of dsPIC33FJ06GS001-I/SO
Rohs
yes
Core
dsPIC33F
Data Bus Width
16 bit
Program Memory Size
6 KB
Data Ram Size
256 B
Device Million Instructions Per Second
40 MIPs
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Package / Case
SOIC-18
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
3.0
ICSP mode is a special programming protocol that
allows you to read and write to dsPIC33F device family
memory. The ICSP mode is the most direct method
used to program the device, which is accomplished by
applying control codes and instructions serially to the
device using the PGECx and PGEDx pins. ICSP mode
also has the ability to read executive memory to deter-
mine if the programming executive is present and to
write the programming executive to executive memory
if Enhanced ICSP (E-ICSP) mode will be used.
In ICSP mode, the system clock is taken from the
PGECx pin, regardless of the device’s oscillator Con-
figuration bits. All instructions are shifted serially into an
internal buffer, then loaded into the instruction register
and executed. No program fetching occurs from inter-
nal memory. Instructions are fed in 24 bits at a time.
PGEDx is used to shift data in, and PGECx is used as
both the serial shift clock and the CPU execution clock.
DS70659B-page 6
Note 1: During ICSP operation, the operating
2: ICSP mode is slower then Enhanced
DEVICE PROGRAMMING –
ICSP
frequency of PGECx must not exceed
5 MHz.
ICSP mode for programming.
3.1
Figure 3-1
programming process. After entering ICSP mode, the
first action is to Bulk Erase program memory. Next, the
code memory is programmed, followed by the device
Configuration words. Code memory (including the
Configuration words) is then verified to ensure that pro-
gramming was successful. Then, program the
code-protect Configuration bits, if required.
FIGURE 3-1:
Overview of the Programming
Process
illustrates the high-level overview of the
Verify Program Memory
Program Code-protect
Configuration Words
Configuration Words
Configuration Bits
Program Memory
Enter ICSP™
Perform Bulk
Exit ICSP
HIGH-LEVEL ICSP™
PROGRAMMING FLOW
© 2011 Microchip Technology Inc.
Erase
Start
and
End
and