ADG3242BRJ-R2 Analog Devices Inc, ADG3242BRJ-R2 Datasheet - Page 10

• Manufacturer Part Number: ADG3242BRJ-R2
• Description: IC SW BUS CTRL 2.5/3.3V SOT23-8
• Manufacturer: Analog Devices Inc
• Type: Bus Switchr

Specifications of ADG3242BRJ-R2

• Rohs Status: RoHS non-compliant
• Circuit: 2 x 1:1
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Operating Temperature: -
• Current - Output High, Low: -
• Other names: ADG3242BRJ-R2CT

ADG3242
TERMINOLOGY
V
Positive power supply voltage.
GND
Ground (0 V) reference.
V
Minimum input voltage for Logic 1.
V
Maximum input voltage for Logic 0.
I
Input leakage current at the control inputs.
I
Off state leakage current. It is the maximum leakage current at
the switch pin in the off state.
I
On state leakage current. It is the maximum leakage current at
the switch pin in the on state.
V
Maximum pass voltage. The maximum pass voltage relates to
the clamped output voltage of an NMOS device when the switch
input voltage is equal to the supply voltage.
R
Ohmic resistance offered by a switch in the on state. It is measured
at a given voltage by forcing a specified amount of current through
the switch.
ΔR
On resistance match between any two channels, that is, R
to R
C
Off switch capacitance.
C
On switch capacitance.
I
OZ
OL
ON
X
X
CC
INH
INL
P
ON
OFF
ON
ON
min.
ON
max
Rev. A | Page 10 of 16
C
Control input capacitance. This consists of BE and SEL .
I
Quiescent power supply current. This current represents the
leakage current between the V
when all control inputs are at logic high or low level and the
switches are off.
ΔI
Extra power supply current component for the EN control input
when the input is not driven at the supplies.
t
Data propagation delay through the switch in the on state. Propaga-
tion delay is related to the RC time constant R
is the load capacitance.
t
Bus enable times. These are the times taken to cross the V
response to the control signal, BE .
t
Bus disable times. These are the times taken to place the switch
in the high impedance off state in response to the control signal.
They are measured as the time taken for the output voltage to
change by V
to the logic level transition at the control input. (See Figure 27
for enable and disable times.)
Max Data Rate
Maximum rate at which data can be passed through the switch.
Channel Jitter
Peak-to-peak value of the sum of the deterministic and random
jitter of the switch channel.
PLH
PZH
PHZ
CC
IN
CC
, t
, t
, t
PHL
PZL
PLZ
Δ
from the original quiescent level, with reference
CC
and ground pins. It is measured
ON
× C
L
, where C
T
in
L