ATA3742_07 ATMEL [ATMEL Corporation], ATA3742_07 Datasheet - Page 17

• Manufacturer Part Number: ATA3742_07
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

5.2.4
5.3
5.3.1
4900B–RKE–11/07
Receiving Mode
Duration of the Bit Check
Digital Signal Processing
Figure 5-5 on page 16
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during T
that period. When the bit check becomes active, the bit check counter is clocked with the cycle
T
Figure 5-5 on page 16
is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
ure 5-6 on page
bit check also fails if CV_Lim reaches Lim_max. This is illustrated in
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator
delivers random signals. The bit check is a statistical process and T
Therefore, an average value for T
depends on the selected baud rate range and on T
value for T
In the presence of a valid transmitter signal, T
nal, f
in a longer period for T
If the bit check is successful for all bits specified by N
mode. As shown in
that case. A connected microcontroller can be woken up by the negative edge at pin DATA. The
receiver stays in that condition until it is switched back to polling mode explicitly.
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and
as a result converted into the output signal data. This processing depends on the selected baud
rate range (BR_Range).
extended clock cycle T
state only after T
always an integral multiple of T
The minimum time period between two edges of the data signal is limited to t
implies an efficient suppression of spikes at the DATA output. At the same time, it limits the max-
imum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller. T
t
is frozen for the time period T
T
The maximum time period for DATA to be Low is limited to T
finite response time during programming or switching off the receiver via pin DATA. T
is thereby longer than the maximum time period indicated by the transmitter data stream.
5-10
ee
XClk
DATA_min
as illustrated in
.
Sig
gives an example where Dem_out remains Low after the receiver is in receiving mode.
, and on the count of the checked bits, N
= tmin2 is the relevant stable time period.
Bitcheck
16, the bit check fails as the value CV_lim is lower than the limit Lim_min. The
Startup
XClk
resulting in a lower current consumption in polling mode.
DATA_min
Figure
Figure 5-4 on page
elapses. The edge-to-edge time period t
. The output of the ASK/FSK demodulator (Dem_out) is undefined during
Bitcheck
XClk
shows how the bit check proceeds if the bit check counter value CV_Lim
to
Figure 5-8 on page 18
is to some extent affected by the preceding edge-to-edge time interval
5-9. If t
. This clock is also used for the bit check counter. Data can change its
Figure 5-7
requiring a higher value for the transmitter preburst T
DATA_min
XClk
ee
.
is in between the specified bit check limits, the following level
Bitcheck
= tmin1, in case of t
illustrate the bit check for the default bit check limits
16, the internal data signal is switched to pin DATA in
is given in the electrical characteristics. T
Bitcheck
Bitcheck
illustrates how Dem_out is synchronized by the
Clk
is dependent on the frequency of that sig-
. A higher value for N
. A higher baud rate range causes a lower
Bitcheck
ee
, the receiver switches to receiving
DATA_L_max
being outside that bit check limits
ee
of the data signal as a result is
Bitcheck
Figure
. This function ensures a
varies for each check.
Bitcheck
5-7.
ee
ATA3742
thereby results
T
Preburst
DATA_min
DATA_L_max
.
Bitcheck
Figure
. This
Fig-
17