ATA3742_07 ATMEL [ATMEL Corporation], ATA3742_07 Datasheet - Page 13

• Manufacturer Part Number: ATA3742_07
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

5.2.1
5.2.2
5.2.3
4900B–RKE–11/07
Sleep Mode
Bit-check Mode
Configuring the Bit Check
The length of period T
sion factor X
calculated to be:
T
In US and European applications, the maximum value of T
to “1”. The time resolution is about 2 ms in that case. The sleep time can be extended to almost
half a second by setting X
resulting in a different mode of action as described below:
X
X
as every bit check is OK. If the bit check fails once, this bit is set back to “0”, automatically result-
ing in a regular sleep time. This functionality can be used to save current in the presence of a
modulated disturber similar to an expected transmitter signal. The connected microcontroller is
rarely activated in that condition. If the disturber disappears, the receiver switches back to regu-
lar polling and is again sensitive to appropriate transmitter signals.
The highest register value of Sleep sets the receiver into a permanent sleep condition (see
Table 5-6 on page
programmed into the OPMODE register. This function is desirable where several devices share
a single data line.
In bit-check mode, the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a pro-
grammable time window. The maximum count of these edge-to-edge tests, before the receiver
switches to receiving mode, is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one
bit. This is valid for Manchester, bi-phase and most other modulation schemes. The maximum
count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N
register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N
higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence
of a valid transmitter signal, the bit check takes less time if N
ing mode, the bit check time is not dependent on N
example where 3 bits are tested successfully and the data signal is transferred to pin DATA.
According to
If the edge-to-edge time t
check limit T
T
Sleep
Lim_max
SleepStd
SleepTemp
= Sleep
, the bit check will be terminated and the receiver switches to sleep mode.
= 1 implies the standard extension factor. The sleep time is always extended.
= 1 implies the temporary extension factor. The extended sleep time is used as long
Figure
Lim_max
Sleep
X
Sleep
according to
22). The receiver remains in that condition until another value for Sleep is
, the check will be continued. If t
5-2, the time window for the bit check is defined by two separate time limits.
Sleep
1024
is defined by the 5-bit word Sleep of the OPMODE register, the exten-
ee
Sleep
is in between the lower bit check limit T
to 8. X
T
Table 5-7 on page
Clk
Sleep
can be set to 8 by bit X
Bitcheck
22, and the basic clock cycle T
ee
is smaller than T
Bitcheck
.
Sleep
Figure 5-1 on page 11
is about 60 ms if X
is set to a lower value. In poll-
SleepStd
Lim_min
Bitcheck
Lim_min
or by bit X
and the upper bit
ATA3742
Bitcheck
in the OPMODE
or t
ee
Sleep
is set to a
shows an
SleepTemp
exceeds
Clk
. It is
is set
13
,