COREDES-AR ACTEL [Actel Corporation], COREDES-AR Datasheet
COREDES-AR
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COREDES-AR Summary of contents
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... Continue • Simulation: OVI-Compliant Verilog Simulators and Vital-Compliant VHDL Simulators Core Verification • Actel-Developed Simulation Testbench Verifies CoreDES against Tests Listed in the National Institute of Standards and Technology (NIST) Special Publication 800-17, Modes of Operation Validation System (MOVS): Requirements and Procedures • Users Can Easily Modify Testbench Using Existing ...
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... Permutation Output Figure 1 • DES Algorithm 2 General Description The CoreDES macro implements the Data Encryption Standard (DES), which provides a means of securing data. The DES algorithm is described in Processing Standards (FIPS) Publication (PUB) algorithm takes as input 64 bits of plaintext data and 64 bits of a cipher key (only 56 of the 64 bits of the key are ...
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... Cipher Key schedule logic Parity check logic RT54SX-S) employ FuseLock provides a means to keep the cipher key and the rest of the logic secure. The output of the CoreDES macro should be connected to registers or FIFOs only valid for sections"Encryption" on page 6 TM page 7, respectively. technology, ...
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... CoreDES CoreDES Device Requirements The CoreDES macro has been implemented in several of the Actel device families. A summary of the implementation data is listed in Table 1. Table 1 • CoreDes Device Utilization and Performance Cells or Tiles Family Sequential Combinatorial Fusion 148 ProASIC3/E 148 PLUS ProASIC 142 Axcelerator ...
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... I/O Signal Descriptions The port signals for the CoreDES macro are defined in Table 2 and illustrated in Figure 4. CoreDES has 200 I/O signals that are described in Table 2. All arrayed ports are labeled with indices that begin with the number 1 (most significant bit) and ascend up to the width of the arrayed Table 2 • ...
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... CoreDES Encryption To begin the process of encrypting data, the following inputs are set: 1. K[1:64] is set to the cipher key (ck1 in encrypt the data. 2. D[1:64] is set to the plaintext data ( encrypted set to logic '1 set to logic '1'. cycle 1 CLK K[1:64] ck1 D[1:64 Q[1:64] QVAL Figure 6 • ...
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... QVAL signal will transition from logic '0' to logic '1' and remain valid for Figure 7) to one clock (unencrypted data shown as q1 Figure 7) the Q[1:64] outputs v4.0 CoreDES cycle, indicating that valid plaintext Figure 7) is available on q1 Undefined Don't care 7 ...
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... FIFO, the user may want to pause the CoreDES macro by setting the EN input to a logic '0' when the full or almost-full flag logic from the FIFO is active. When the FIFO full or almost-full flag logic clears, the CoreDES macro can then resume operation by again setting the EN input to a logic '1' value ...
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... CLR input at a logic '1' value for at least one clock cycle, and commence immediately on the following clock cycle with a new cipher key and/or new data. If the CoreDES macro is integrated into a system containing a processor, the processor may want to abort the encryption or decryption operation for some specific event (e ...
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... State's International Traffic in Arms Regulations, or other laws, government regulations, or restrictions. Actel is currently in the process of obtaining additional permissions to ship CoreDES to a wider audience. The licensee will not import, export, reexport, divert, transfer, or disclose CoreDES without complying strictly with the export control laws and all legal requirements in the relevant jurisdictions, including and without limitation, obtaining the prior approval of the U ...
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... This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. was updated to include Fusion. was updated to include ProASIC3/E. was added. v4.0 CoreDES Page ...
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