COREDES-AN Actel Corporation, COREDES-AN Datasheet

COREDES-AN

Manufacturer Part Number

COREDES-AN

Description

Coredes

Manufacturer

Actel Corporation

Datasheet

1.COREDES-AN.pdf (12 pages)

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CoreDES

Product Summary

Intended Use

Key Features

Supported Families

December 2005

• Whenever Data is Transmitted across an Accessible

• E-Commerce

• Personal Security Devices

• Bank Transactions, where Financial Security is

• 56-bit Cipher Key (with 8 Additional Parity Bits)

• Parity Checking Logic for Cipher Key

• Encryption and Decryption Possible with Same

• 16-Clock Cycle Operation to Encrypt or Decrypt 64

• Pause/Resume

• Compliant with FIPS PUB 46-3

• ECB (Electronic Codebook) Implementation per

• Example Source Code Provided for CBC, CFB and

• Provides Data Security within a Secure Actel FPGA

• All Major Actel Device Families Supported

• Fusion

• ProASIC3/E

• ProASIC

• Axcelerator

• RTAX-S

• SX-A

• RTSX-S

Medium (Wires, Wireless, etc.)

Encryption/Decryption Hardware Can Ease the

Load on Servers

Mandatory

Core

Bits of Data

Encryption or Decryption at Will

FIPS PUB 81

OFB Modes

PLUS

Transactions,

Functionality

where

Dedicated

Continue

v 4 .0

Core Deliverables

Synthesis and Simulation Support

Core Verification

• Evaluation Version

• Netlist Version

• RTL Version

• Actel-Developed Testbench (Verilog and VHDL)

• Synthesis:

• Simulation: OVI-Compliant Verilog Simulators and

• Actel-Developed Simulation Testbench Verifies

• Users Can Easily Modify Testbench Using Existing

– Compiled

– Structural Verilog and VHDL Netlists (with and

– Compiled

– Verilog or VHDL Core Source Code

– Core Synthesis Scripts

Compiler

Exemplar

Vital-Compliant VHDL Simulators

CoreDES against Tests Listed in the National

Institute of Standards and Technology (NIST)

Special Publication 800-17, Modes of Operation

Validation System (MOVS): Requirements and

Procedures

Format to Add More Tests Listed in NIST Special

Publication 800-17 or Custom Tests

Supported in the Actel Libero

Design Environment (IDE)

without I/O pads) Compatible with the Actel

Designer Place-and-Route Software Tool

Supported in the Actel Libero IDE

™

/ FPGA Compiler

Synplicity

RTL

Simulation

™

Synopsys

/ FPGA Express

Model

Integrated

(Design

Fully

™

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