EM565161BJ-70 Etron Technology Inc., EM565161BJ-70 Datasheet
EM565161BJ-70
Manufacturer Part Number
EM565161BJ-70
Description
Manufacturer
Etron Technology Inc.
Datasheets
1.EM565161.pdf
(13 pages)
2.EM565161BJ-70.pdf
(13 pages)
3.EM565161BJ-70.pdf
(13 pages)
4.EM565161BJ-70.pdf
(13 pages)
Specifications of EM565161BJ-70
Case
BGA
Date_code
04+
EtronT ech
Features
• Single Power Supply Voltage, 2.3 ~ 3.6 V
• Power Down Features Using CE1#, CE2, LB# and
• Low Power Dissipation
• Data retention Supply Voltage: 1.0V to 3.6V
• Direct TTL Compatibility for All Input and Output
• Wide Operating Temperature Range: -40°C to 85°C
• Standby current (maximum) @ VDD = 3.6 V
Ordering Information
Overview
The EM565161 is an 8M-bit SRAM organized as 512K words by 16 bits. It is designed with advanced CMOS
technology. This Device operates from a single power supply. Advanced circuit technology provides both high
speed and low power. It is automatically placed in low-power mode when CE1# or both UB# and LB# are
asserted high or CE2 is asserted low. There are three control inputs. CE1# and CE2 are used to select the
device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control
pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor
system applications where high speed, low power and battery backup are required. And, with a guaranteed
operating range from –40°C to 85°C, the EM565161 can be used in environments exhibiting extreme
temperature conditions.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
UB#
Part Number
EM565161BA/BJ-55
EM565161BA/BJ-70
EM565161BA/BJ-55E/70E
Part Number
EM565161BJ-70
EM565161BA-70
EM565161BA-70E
EM565161BJ-55
EM565161BA-55
EM565161BA-55E
Speed
70 ns
70 ns
70 ns
55 ns
55 ns
55 ns
Typical
14 µA
2 µA
2 µA
FAX: (886)-3-5778671
I
25 µA
25 µA
80 µA
35 µA
35 µA
80 µA
DDS2
I
DDS2
Package
6x9 BGA
8x10 BGA
8x10 BGA
6x9 BGA
8x10 BGA
8x10 BGA
Maximum
35 µA
25 µA
80 µA
Pin Assignment
48-Ball BGA (CSP), Top View
Pin Names
C
D
G
H
A
B
E
F
Symbol
A0 – A18
DQ0-DQ15
CE1#,CE2
OE#
WE#
LB#,UB#
GND
V
NC
DD
512K x 16 Low Power SRAM
D Q 1 4
D Q 1 5
G N D
D Q 8
D Q 9
V D D
A 1 8
L B #
1
D Q 1 1
D Q 1 0
D Q 1 2
D Q 1 3
O E #
U B #
N C
A 8
2
Preliminary, Rev 0.9 01/2002
Function
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable
Read/Write Control Input
Data Byte Control Inputs
Ground
Power Supply
No Connection
G N D
A 1 7
A 1 4
A 1 2
A 0
A 3
A 5
A 9
3
A 1 6
A 1 5
A 1 3
A 1 0
A 7
A 1
A 4
A 6
4
EM565161
C E 1 #
W E #
D Q 1
D Q 3
D Q 4
D Q 5
A 1 1
A 2
5
G N D
D Q 0
D Q 2
V D D
D Q 6
D Q 7
C E 2
N C
6
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