AM53CF94JCW AMD [Advanced Micro Devices], AM53CF94JCW Datasheet - Page 23

• Manufacturer Part Number: AM53CF94JCW
• Description: Enhanced SCSI-2 Controller (ESC)
• Manufacturer: AMD [Advanced Micro Devices]

SCSI Timeout Register (05H) Write
SCSI Timeout Register
STIMREG
This register determines how long the Initiator (Target)
will wait for a response to a Selection (Reselection)
before timing out. It should be set to yield 250 ms to
comply with ANSI standards for SCSI, but the maximum
time out period may be calculated using the following
formulas.
Note: A hardware reset will clear this register.
Internal State Register (06H) Read
The Internal State Register (ISREG) tracks the progress
of a sequence-type command. It is updated after each
successful completion of an intermediate operation. If
an error occurs, the host can read this register to
determine the point where the command failed and take
the necessary procedure for recovery. Reading the
Interrupt Status Register (INSTREG) while an interrupt
is pending will clear this register. A hard or soft reset will
also zero this register .
ISREG – Bits 7:4 – RES – Reserved
STIM7
7
x
STIM6
6
x
STIM5
5
x
Internal State Register
ISREG
STIM4
RES
7
x
4
x
STIM3
RES
6
x
3
x
STIM2
RES
5
x
2
x
RES
STIM1
4
x
1
x
Address: 05
Type: Write
Am53CF94/Am53CF96
P R E L I M I N A R Y
17348B-23
SOF
STIM0
3
0
0
x
H
IS2
2
0
IS1
STIMREG – Bits 7:0 – STIM 7:0 – SCSI Timer 7:0
The value loaded in STIM 7:0 can be calculated as
shown below:
STIM 7:0 =
[(SCSI Time Out) (Clock Frequency) / (8192 (Clock
Factor))]
Example:
SCSI Time Out (in seconds): 250 ms. (Recommended
by the ANSI Standard) = 250 x 10
Clock Frequency: 20 MHz. (assume) = 20 x 10
Clock Factor: CLKF 2:0 from Clock Conversion Register
(09H) = 5
STIM 7:0 = (250 x 10
decimal
ISREG – Bit 3 – SOF – Synchronous Offset Flag
The SOF is reset when the Synchronous Offset Register
(SOFREG) has reached its maximum value.
Note:
The SOF bit is active Low.
ISREG – Bits 2:0 – IS 2:0 – Internal State 2:0
The IS 2:0 bits along with the Interrupt Status Register
(INSTREG) indicates the status of the successfully
completed intermediate operation. Refer to the Status
Decode section for more details.
1
0
Address: 06
Type: Read
IS0
0
0
H
Internal State 2:0
Synchronous Offset Flag
Reserved
Reserved
Reserved
Reserved
–3
) X (20 x 10
17348B-24
–3
6
) / (8192 (5)) = 122
s.
AMD
6
Hz.
23