HS9-82C85RH-8 INTERSIL [Intersil Corporation], HS9-82C85RH-8 Datasheet
HS9-82C85RH-8
Related parts for HS9-82C85RH-8
HS9-82C85RH-8 Summary of contents
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... Ordering Information INTERNAL ORDERING NUMBER MKT. NUMBER 5962R9582001VJC HS1-82C85RH-Q 5962R9582001VXC HS9-82C85RH-Q HS9-82C85RH/Proto HS9-82C85RH/Proto 1 1-888-INTERSIL or 321-724-7143 August 2000 Features • Electrically Screened to SMD # 5962-95820 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Hardened - Total Dose 100 krad(Si) (Max) - Transient Upset . . . . . . . . . . . . . . . . . . . . >10 - Latch Up Free EPI-CMOS • ...
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Pinouts 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW CSYNC 1 PCLK 2 AEN1 3 RDY1 4 READY 5 RDY2 6 AEN2 7 CLK 8 GND 9 CLK50 10 START 11 SLO/FST 12 Pin Descriptions PIN ...
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Pin Descriptions (Continued) PIN PIN NUMBER TYPE SLO/FST 12 I SLO/FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the maximum frequency (crystal or EFI frequency divided by 3). When LOW, CLK and CLK50 frequencies ...
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Functional Diagram RES (17) RESTART START (11) CSYNC (1) SLO/FST (12) F/C (19) EXTERNAL FREQUENCY SELECT EFI (20) X2 (22) OSCILLATOR X1 (23) S2/STOP (15) S1 (14) SO (13) RDY1 (4) AEN1 (3) SELECT AEN2 (7) RDY2 (6) ASYNC (21) ...
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Waveforms EFI I t ELEH t EHEL OSC O t OHCH CLK O CLK50 O PCLK O t YHEH t EHYL CSYNC I t YHYL NOTE: All timing measurements are made at 1.5V, unless otherwise noted. CLK t CLR1X t ...
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Waveforms (Continued) CLK t R1VCL RDY1 A1VR1V AEN1, 2 ASYNC READY FIGURE 3. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES) EFI CLK CLK50 PCLK S0 t CHSX t SVCH S1 S2/STOP RES t RSVCH START 6 HS-82C85RH t ...
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Waveforms (Continued) EFI CLK CLK50 PCLK S0 S1 S2/STOP RES START t SHSL START OSC CRYSTAL OSCILLATOR STARTUP TIME CLK CLK50 PCLK RES CLK RESET FIGURE 7. RESET TIMING (CLK RUNNING WITH F/C LOW - OSC MODE; CLK RUNNING - ...
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Waveforms (Continued) RES CLK RESET OSC STARTUP TIME OSC FIGURE 8. RESET TIMING OSCILLATOR STOPPED (F/C LOW) NOTE: CLK, CLK50, PCLK remain in the high state until RES goes high and 8192 valid oscillator cycles have been registered by the ...
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Waveforms (Continued) EFI OR OSC PCLK SLO/FST CLK CLK50 NOTE not met on one edge of PCLK, SLO/FST will be recognized on the next edge of PCLK. SFPC CLK 15MHz CLK50 ...
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Burn-In Circuits STATIC CONFIGURATION NOTES 10k 10 6.0V 5%. DD ...
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Functional Description The HS-82C85RH Static Clock Controller/Generator provides simple and complete control of static CMOS system operating modes. The HS-82C85RH can operate with either an external crystal or an external frequency source and can support full speed, slow, stop-clock and ...
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Oscillator/Clock Start Control Once the oscillator is stopped (or committed to stop power-on, the restart sequence is initiated by a HIGH state on START or LOW state on RES. If F/C is HIGH, then restart occurs immediately after ...
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The HS-82C85RH status inputs S2/STOP, S1, S0 are sampled on the rising edge of CLK. The oscillator (F/C LOW only) and clock outputs are stopped by S2/STOP, S1, S0 being in the LHH state on a low-to-high transition of CLK. ...
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Internal logic requires that the SLO/FST pin be held low for at least 195 oscillator or EFI clock pulses before the SLOW mode command is recognized. This requirement eliminates unwanted FAST-to-SLOW mode frequency changes which could be caused by glitches ...
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TABLE 3. CRYSTAL SPECIFICATIONS PARAMETER TYPICAL CRYSTAL SPECIFICATION Frequency 2.4MHz to 15MHz Type of Operation Parallel Resonant, Fund. Mode Load Capacitance 20pF or 32pF R Series (Max 15MHz, C 105 (f = 15MHz, C Frequency Source Selection ...
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Die Characteristics DIE DIMENSIONS: 2770 m x 3130 m x 483 INTERFACE MATERIALS: Glassivation: Type: SiO2 Å Å Thickness Top Metallization: Type: Al/Si Å Å Thickness: 11k 2k Metallization Mask Layout RDY1 (4) READY (5) ...