HS9-80C85RH INTERSIL [Intersil Corporation], HS9-80C85RH Datasheet

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HS9-80C85RH

Manufacturer Part Number
HS9-80C85RH
Description
Radiation Hardened 8-Bit CMOS Microprocessor
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
February 1996
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Devices QML Qualified in Accordance With
• Detailed Electrical and Screening Requirements are
• Radiation Hardened EPI-CMOS
• Low Standby Current 500 A Max
• Low Operating Current 5.0mA/MHz (X
• Electrically Equivalent to Sandia SA 3000
• 100% Software Compatible with INTEL 8085
• Operation from DC to 2MHz, Post Radiation
• Single 5 Volt Power Supply
• On-Chip Clock Generator and System Controller
• Four Vectored Interrupt Inputs
• Completely Static Design
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55
Pinouts
MIL-PRF-38535
Contained in SMD# 5962-95824 and Intersil’ QM Plan
- Parametrics Guaranteed 1 x 10
- Transient Upset > 1 x 10
- Latch-up Free > 1 x 10
RESET OUT
RST 7.5
RST 6.5
RST 5.5
40 LEAD CERAMIC DUAL-IN-LINE
TRAP
METAL SEAL PACKAGE (SBDIP)
INTR
INTA
GND
SOD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
SID
X1
X2
MIL-STD-1835, CDIP2-T40
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
TOP VIEW
12
|
8
Copyright
RAD(Si)/s
RAD(Si)/s
o
C to +125
5
40
39
38
37
36
35
34
32
31
30
29
28
27
26
25
24
23
22
21
33
©
RAD(Si)
VDD
HOLD
HLDA
CLOCK OUT
RESET IN
READY
IO / M
S1
RD
WR
ALE
S0
A15
A14
A13
A12
A11
A10
A9
A8
Intersil Corporation 1999
1
Input)
o
C
1
HS-80C85RH
Description
The HS-80C85RH is an 8-bit CMOS microprocessor fabri-
cated using the Intersil radiation hardened self-aligned junc-
tion isolated (SAJI) silicon gate technology. Latch-up free
operation is achieved by the use of epitaxial starting material
to eliminate the parasitic SCR effect seen in conventional
bulk CMOS devices.
The HS-80C85RH is a functional logic emulation of the
HMOS 8085 and its instruction set is 100% software com-
patible with the HMOS device. The HS80C85RH is designed
for operation with a single 5 volt power supply. Its high level
of integration allows the construction of a radiation hardened
microcomputer system with as few as three ICs (HS-
80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/
56RH RAM I/O.
RST 7.5
RST 6.5
RST 5.5
RESET
TRAP
INTR
INTA
SOD
OUT
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
SID
NC
NC
X1
X2
FLATPACK PACKAGE (FLATPACK)
42 LEAD CERAMIC METAL SEAL
8-Bit CMOS Microprocessor
INTERSIL OUTLINE K42.A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TOP VIEW
Radiation Hardened
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Spec Number
File Number
CLOCK
OUT
VDD
HOLD
HLDA
RESET
READY
IO / M
S1
RD
WR
ALE
S0
A15
A14
A13
A12
A11
A10
A9
A8
GND
IN
518054
3036.2

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HS9-80C85RH Summary of contents

Page 1

February 1996 Features • Devices QML Qualified in Accordance With MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95824 and Intersil’ QM Plan • Radiation Hardened EPI-CMOS - Parametrics Guaranteed Transient Upset ...

Page 2

... Ordering Information PART NUMBER TEMPERATURE RANGE 5962R9582401QQC -55 5962R9582401QXC -55 5962R9582401VQC -55 5962R9582401VXC -55 HS1-80C85RH/SAMPLE HS9-80C85RH/SAMPLE Functional Diagram INTR INTERRUPT CONTROL ACCUMU- TEMP REG LATOR (8) (8) VDD POWER SUPPLY GND X1 CLK CONTROL GEN X2 READY CLK RD OUT HS-80C85RH SCREENING LEVEL +125 C MIL-PRF-38535 Level ...

Page 3

Pin Description PIN SYMBOL NUMBER TYPE A8 - A15 21-28 O Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address, 3-stated during Hold and Halt modes and during RESET. AD0-7 ...

Page 4

Pin Description (Continued) PIN SYMBOL NUMBER TYPE INTR 10 I INTA 11 O RST 5 RST 6.5 8 RST 7.5 7 TRAP 6 I RESET RESET OUT ...

Page 5

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER A8-15 Valid Before Trailing Edge of ALE (Note 5) A0-7 Valid Before Trailing Edge of ALE READY Valid from Address Valid Address (A8-15) Valid After Control Width of Control Low (RD, WR, ...

Page 7

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Input Capacitance CIN I/O Capacitance CI/O Output Capacitance COUT NOTE: 1. All measurements referenced to device ground. TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The post irradiation test conditions and limits ...

Page 8

Waveforms X INPUT 1 CLK OUTPUT tXKR tXKF CLK A 8- tLL ALE tAL RD/INTA T1 CLK A ADDRESS 8-15 AD -AD ADDRESS 0 7 tLL ALE tAL WR tAC HS-80C85RH tCYC FIGURE ...

Page 9

Waveforms (Continued) T2 CLK HOLD tHDS HLDA BUS (ADDRESS, CONTROLS) T1 CLK tLCK A ADDRESS 8-15 AD -AD ADDRESS 0 7 tLA tLL ALE tAL tLC RD/INTA tLRY tAC tARY READY NOTE 1: READY MUST REMAIN STABLE DURING SETUP AND ...

Page 10

INSTRUCTION CODE MNEMONIC MOVE, LOAD, AND STORE MOVr1 MOV M MOV ...

Page 11

TABLE 9. INSTRUCTION SET SUMMARY (Continued) INSTRUCTION CODE MNEMONIC JPE JPO PCHL ...

Page 12

Functional Description The HS-80C85RH is a complete 8-bit parallel central pro- cessing unit implemented in a self aligned, silicon gate, CMOS technology. Its static design allows the device to be operated at any external clock frequency from a maximum of ...

Page 13

INSIDE THE EXTERNAL 80C85RH TRAP INTERRUPT REQUEST TRAP RESET IN SCHMITT RESET TRIGGER D VDD CLEAR TRAP F.F. INTERNAL TRAP ACKNOWLEDGE FIGURE 8. TRAP AND RESET IN CIRCUIT The TRAP interrupt is special in that is disables interrupts, but preserves ...

Page 14

HS-80C85RH Caveats 1. An important caveat that is applicable to CMOS devices in gen- eral is that unused inputs should never be left floating. This rule also applies to inputs connected to a tri- state bus. The need for external ...

Page 15

HS-80C85RH A8-15 AD0-7 ALE RD HS-80C85RH WR IO/M CLK RESET OUT READY TIMER OUT HS-81C56RH (RAM + I/O + COUNTER/TIMER) (6) (8) FIGURE 13. HS-80C85RH MINIMUM SYSTEM (MEMORY MAPPED I/ TRAP RST 7.5 RST 6.5 HS-80C85RH RST 5.5 ...

Page 16

Basic System Timing The HS-80C85RH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 15 shows an instruction fetch, memory read and I/O write cycle (as ...

Page 17

Metallization Topology DIE DIMENSIONS: 229 mils x 240 mils x 14 mils 1 mil METALLIZATION: Type: SiAl Å Å Thickness: 11k 2k GLASSIVATION: Type: SiO 2 Å Å Thickness Metallization Mask Layout TRAP (6) RST 7.5 (7) RST ...

Page 18

Packaging LEAD FINISH BASE METAL (b) SECTION A-A NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one ...

Page 19

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, ...

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