MT16VDDF12864HG-202 MICRON [Micron Technology], MT16VDDF12864HG-202 Datasheet
MT16VDDF12864HG-202
Related parts for MT16VDDF12864HG-202
MT16VDDF12864HG-202 Summary of contents
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... Address Table Refresh Count Device Row Addressing Device Bank Addressing Device Configuration Device Column Addressing Module Rank Addressing 09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 512MB, 1GB (x64) 200-PIN DDR SODIMM MT16VDDF6464H – 512MB MT16VDDF12864H – ...
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... MT16VDDF6464HY-202__ MT16VDDF12864HG-335__ MT16VDDF12864HY-335__ MT16VDDF12864HG-262__ MT16VDDF12864HY-262__ MT16VDDF12864HG-26A__ MT16VDDF12864HY-26A__ MT16VDDF12864HG-265__ MT16VDDF12864HY-265__ MT16VDDF12864HG-202__ MT16VDDF12864HY-202__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current Revision codes. Example: MT16VDDF6464HG-265A1. 09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN CONFIGURATION TRANSFER 512MB ...
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... 193 SDA 44 DD DQ41 195 SCL 46 DQS5 197 SPD V 199 Figure 2: Module Layout Front View U17 (all odd pins) PIN 199 PIN 1 Back View U11 U12 U13 U14 U9 U13 U16 (all even pins) ...
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... V Input SSTL_2 reference voltage. REF SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to ...
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... DDSPD NC — No Connect: These pins should be left unconnected. DNU — Do Not Use: These pins are not connected on this module, but are assigned pins on other modules in this product family. 5 512MB, 1GB (x64) 200-PIN DDR SODIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... CKE0 CKE1 WE# SERIAL PD SCL WP A0 SA0 NOTE: 1. All resistor values are 22 W unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at numberguide. 09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN DQS1 DM1 DM CS# DQS DQ DQ8 DQ DQ9 ...
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... CKE0: DDR SDRAMs U1-U8 CKE1 CKE1: DDR SDRAMs U9-U16 WE#: DDR SDRAMs WE# NOTE: 1. All resistor values are 22 W unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at numberguide. 09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN DQS1 DM1 DM CS# DQS DQ ...
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... The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be pro- grammed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer ...
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Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being program- mable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode regis- ter (BA0/ ...
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Commands The Truth Tables below provides a general reference of available commands. For a more detailed descrip- Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) DESELECT (NOP) NO OPERATION (NOP) ACTIVE ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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... (MIN); Address and control inputs change only during Active READ, or WRITE commands NOTE Value calculated as one module rank in this operating condition, and all other module ranks Value calculated reflects all module ranks in this operating condition. 09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN ...
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... (MIN); Address and control inputs change only during Active READ, or WRITE commands NOTE Value calculated as one module rank in this operating condition, and all other module ranks Value calculated reflects all module ranks in this operating condition. 09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN ...
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Table 14: Capacitance Note: 11; notes appear notes appear on pages 20–23 PARAMETER Input/Output Capacitance: DQ, DQS,DM Input Capacitance: Command and Address, RAS#, CAS#, WE# Input Capacitance:CK, CK#, CKE, S# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC ...
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Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°C £ CHARACTERISTICS PARAMETER ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°C £ CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued) Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°C £ CHARACTERISTICS PARAMETER DQS read preamble DQS read postamble ACTIVE bank ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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CK that meets the maximum absolute t value for RAS. 21. The refresh period 64ms. This equates to an aver- age refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every ...
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HP min is the lesser of CL minimum and minimum actually applied to the device CK and CK# inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not t allowed to be issued ...
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... DLL is required to be reset. This is followed by 200 clock cycles. 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. When an input signal is HIGH or LOW defined as a steady state logic HIGH or LOW. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure ...
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Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first. SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential ...
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Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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... Fundamental Memory Type 3 Number of Rows Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of Physical Ranks on DIMM 6 Module Data With 7 Module Data With (Continued) 8 Moduel Voltage Interface Levels 9 t SDRAM Cycle Time, ( CK), CAS Latency = 2.5 (See note 1) 10 SDRAM Access From Clock,( CAS Latency = 2.5 ...
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... Reserved 62 SPD Revision 63 Checksum for Bytes 0-62 64 Manufacturer’s JEDEC ID Code 65-71 Manufacturer’s JEDEC ID Code (Continued) 72 Manufacturing Location 73-90 Module Part Number (ASCII) 91 PCB Identification Code 92 Identification Code (Continued) 93 Year of Manufacture in BCD 09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN ENTRY (VERSION) 42ns (-335) t RAS) 45ns (-262/-26A/-265) ...
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... The value of RAS used for -262/-26A/-265 modules is calculated from 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met ...
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Figure 15: 200-PIN SODIMM Dimensions – 512MB 0.079 (2.00 (2X) 0.071 (1.80) (2X) U7 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (.99) TYP PIN 1 U9 U15 PIN 200 NOTE: All dimensions are in inches (millimeters) 09005aef80a646bc DDF16C64_128x64HG_B.fm ...
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Figure 16: 200-PIN SODIMM Dimensions – 1GB 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) U5 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (.99) TYP PIN 1 U9 U13 PIN 200 NOTE: All dimensions are in inches (millimeters) Data Sheet ...