SMC256BFY6 STMICROELECTRONICS [STMicroelectronics], SMC256BFY6 Datasheet - Page 52

• Manufacturer Part Number: SMC256BFY6
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

CF-ATA registers
9.9
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
52/91
Table 44.
Status & Alternate Status Registers
The Status & Alternate Status registers are located at addresses 1F7h [177h] and 3F6h
[376h], respectively. Offsets are 7h and Eh.
These registers return the Card status when read by the host.
Reading the Status Register clears a pending interrupt. Reading the Auxiliary Status
Register does not clear a pending interrupt.
The Status Register should be accessed in Byte mode; in Word mode it is recommended
that Alternate Status Register is used. The status bits are described as follows
Bit 7 (BUSY)
The busy bit is set when only the Card can access the command register and buffer, The
host is denied access. No other bits in this register are valid when this bit is set to ‘1’.
Bit 6 (RDY)
This bit indicates whether the device is capable of performing CompactFlash Memory Card
operations. This bit is cleared at power up and remains cleared until the Card is ready to
accept a command.
Bit 5 (DWF)
When set this bit indicates a Write Fault has occurred.
Bit 4 (DSC)
This bit is set when the Card is ready.
Bit 3 (DRQ)
The Data Request is set when the Card requires information be transferred either to or from
the host through the Data register. The bit is cleared by the next command.
Bit 2 (CORR)
This bit is set when a Correctable data error has been encountered and the data has been
corrected. This condition does not terminate a multi-sector read operation.
Bit 1 (IDX)
This bit is always set to ‘0’.
D7
1
Drive/Head Register
LBA
D6
D5
1
DRV
D4
HS3
D3
HS2
D2
HS1
D1
SMCxxxBF
HS0
D0