SMC256BFY6 STMICROELECTRONICS [STMicroelectronics], SMC256BFY6 Datasheet - Page 20

• Manufacturer Part Number: SMC256BFY6
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical interface
Table 9.
20/91
READY
(PC Card Memory Mode)
–IREQ
(PC Card I/O Mode)
INTRQ
(True IDE Mode)
–REG
(PC Card Memory Mode)
–REG
(PC Card I/O Mode)
–DMACK
(True IDE Mode)
RESET
(PC Card Memory Mode)
RESET
(PC Card I/O Mode)
–RESET
(True IDE Mode)
V
(PC Card Memory Mode)
V
(PC Card I/O Mode)
V
(True IDE Mode)
CC
CC
CC
Signal Name
Signal Description (continued)
Dir.
O
I
I
13,38
Pin
37
44
41
Indicates whether the Card is busy (Low), or ready to
accept a new data transfer operation (High). The Host
socket must provide a pull-up resistor. At power up and
Reset, the READY signal is held Low until the commands
are completed. No access should be made during this time.
The READY signal is held High whenever the Card has
been powered up with RESET continuously disconnected or
asserted.
Interrupt Request. It is strobed Low to generate a pulse
mode interrupt or held Low for a level mode interrupt.
Active High Interrupt Request to the host.
Used to distinguish between Common Memory and
Register (Attribute) Memory accesses. High for Common
Memory, Low for Attribute Memory.
Must be Low during I/O Cycles when the I/O address is on
the Bus.
The –DMACK input signal is used to acknowledge DMA
transfers. It is asserted by the host in response to DMARQ
to initiate the transfer.
When DMA mode is disabled,
-DMACK signal.
If the host does not support DMA mode, but only True IDE
mode, this signal should be driven High or tied to V
host.
Resets the Card (active High). The Card is Reset at power
up only if this pin is left High or unconnected.
Same as PC Card Memory Mode.
Hardware Reset from the host (active Low).
+5V, +3.3V power.
Same for all modes.
Same for all modes.
Description
the Card should ignore the
SMCxxxBF
CC
by the