K4H560438D-TC SAMSUNG [Samsung semiconductor], K4H560438D-TC Datasheet - Page 15

• Manufacturer Part Number: K4H560438D-TC
• Description: 256Mb
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4H560838D
Overshoot/Undershoot specification
AC Operating Conditions
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
Notes 1. Includes
DDR SDRAM IDD spec table
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
IDD6
2. V
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
2. The value of V
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu
5. The value of V
3. V
Symbol
lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
IDD4W
IDD2Q
V
IDD2P
IDD3P
IDD3N
IDD4R
IDD7A
IDD2F
V
coupled TO V
TT
IDD0
IDD1
IDD5
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
REF
ID
REF
Low power
is not applied directly to the device. V
is the magnitude of the difference between the input level on CK and the input level on CK.
Normal
, and must track variations in the DC level of V
, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
25mV margin for DC offset on V
Parameter/Condition
IX
REF
IX
is expected to equal 0.5*V
is expected to equal 0.5*V
, both of which may result in V
K4H560838D-TC/LB3
(DDR333)
120
170
170
180
325
1.5
90
25
20
35
55
3
3
Parameter
TT
DDQ
DDQ
REF
is a system supply for signal termination resistors, is expected to be set equal to
K4H560838D-TC/LA2, CB0
of the transmitting device and must track variations in the DC level of the same.
, and a combined total of
of the transmitting device and must track variations in the dc level of the same.
REF
REF
(DDR266A/B)
noise. V
- 15 -
32Mx8
110
140
140
165
280
1.5
80
20
18
30
45
VIH(AC)
VID(AC)
Symbol
VIX(AC)
VIL(AC)
3
3
REF
should be de-coupled with an inductance of
0.5*VDDQ-0.2
VREF + 0.31
50mV margin for all AC noise and DC offset on
Min
0.7
K4H560838D-TC/LA0
(DDR200)
100
120
115
150
235
1.5
0.5*VDDQ+0.2
75
18
16
25
40
3
3
VREF - 0.31
VDDQ+0.6
Rev. 0.4 May. 2002
Control pins
Max
Address &
4.5 V-ns
4.5 V-ns
REF
1.6 V
1.6 V
and internal DRAM noise
Specification
(V
DDR SDRAM
DD
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
=2.7V, T = 10
Unit
V
V
V
V
3nH.
Data pins
2.5 V-ns
2.5 V-ns
1.2V
1.2V
Optional
Notes
Note
3
3
1
2
C
)