K4D263238A-GC36 SAMSUNG [Samsung semiconductor], K4D263238A-GC36 Datasheet
K4D263238A-GC36
Related parts for K4D263238A-GC36
K4D263238A-GC36 Summary of contents
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... K4D263238A-GC 128Mbit DDR SDRAM Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL Samsung Electronics reserves the right to change products or specification without notice 32Bit x 4 Banks (144-Ball FBGA) Revision 2.0 January 2003 - 1 - 128M DDR SDRAM Rev. 2.0 (Jan. 2003) ...
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... Changed tCK(max) of K4D263238A-GC40 from 7ns to 10ns. • Changed tCK(max) of K4D263238A-GC33/36 from 5ns to 4ns. Revision 1.5 (December 14, 2001) • Removed K4D26323RA-GC2A/33/36(VDD/VDDQ=2.8V) & K4D263238A-GC55/60 from the spec. • Added K4D263238A-GC36(VDD/VDDQ=2.5V) Revision 1.4 (November 14, 2001) • Added K4D26323RA-GC36(VDD/VDDQ=2.8V) Revision 1.3 (October 22, 2001) • Corrected part number of K4D263238A-GC2A to K4D26323RA-GC2A • ...
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... Differential clock input • No Wrtie-Interrupted by Read Function ORDERING INFORMATION Part NO. K4D263238A-GC33 K4D263238A-GC36 K4D263238A-GC40 K4D263238A-GC45 K4D263238A-GC50 GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238A is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 32 bits, fabricated with SAMSUNG extremely high performance ...
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... K4D263238A-GC PIN CONFIGURATION DQS0 DM0 VSSQ C DQ4 VDDQ NC D DQ6 DQ5 VSSQ E DQ7 VDDQ VDD F DQ17 DQ16 VDDQ DQ19 DQ18 VDDQ G H DQS2 DM2 NC J DQ21 DQ20 VDDQ DQ22 DQ23 VDDQ K CAS WE VDD L RAS BA0 N NOTE: 1. RFU1 is reserved for A12 2 ...
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... K4D263238A-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK*1 Input CKE Input CS Input RAS Input CAS Input WE Input DQS ~ DQS Input/Output Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply ...
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... K4D263238A-GC BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 32 Intput Buffer CK, CK Data Input Register Serial to parallel 64 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
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... K4D263238A-GC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...
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... K4D263238A-GC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
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... K4D263238A-GC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
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... V +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. IH DDQ 5. V (mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate For any pin under test input of 0V < For K4D263238A-GC33/36/40/45/50, V Symbol OUT V DD ...
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... K4D263238A-GC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I P CC2 in Power-down mode Precharge Standby Current I N CC2 in Non Power-down mode Active Standby Current I P CC3 power-down mode Active Standby Current in ...
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... K4D263238A-GC AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output CAPACITANCE (V =2.5V Parameter ...
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... K4D263238A-GC AC CHARACTERISTICS Sym- Parameter bol CL cycle time CL high level width low level width CL t DQS out access time from CK DQSCK t Output access time from Data strobe edge to Dout edge DQSQ t Read preamble RPRE t Read postamble RPST valid DQS-in ...
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... K4D263238A-GC Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...
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... Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) K4D263238A-GC33 Frequency Cas Latency 300MHz ( 3.3ns ) 5 275MHz ( 3.6ns ) 5 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 K4D263238A-GC36 Frequency Cas Latency 275MHz ( 3.6ns ) 5 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 -33 -36 Min Max ...
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... K4D263238A-GC K4D263238A-GC40 Frequency Cas Latency 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 K4D263238A-GC45 Frequency Cas Latency 222MHz ( 4.5ns ) 4/3 200MHz ( 5.0ns ) 3 K4D263238A-GC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 Simplified Timing( CK, CK BA[1:0] BAa BAa Ra A8/AP Ra ADDR (A0~A7 A9,A10) WE DQS DQ Da0 Da1 Da2 Da3 ...
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... K4D263238A-GC PACKAGE DIMENSIONS (144-Ball FBGA) 0.45 0.25 1.40 A1 INDEX MARK 12.0 <Top View> 0.8x11=8.8 0.10 Max 0 ± 0. ± 0.05 Max <Bottom View> 128M DDR SDRAM 12.0 A1 INDEX MARK 0.8 0.40 0.40 Rev. 2.0 (Jan. 2003) Unit : mm ...