PC2700 INFINEON [Infineon Technologies AG], PC2700 Datasheet
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PC2700
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HYS72D32300GBR–[5/ 6/7]–B HYS72D643[ 00/ 20] GBR–[ 5/6/7] –B HYS72D128320GBR–[5/6/ 7]–B 184 - Pi n Regist ered Doubl e Data Rat e SDRAM Modules ...
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Edition 2004-04 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2004. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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HYS72D32300GBR–[5/6/7]–B HYS72D643[00/20]GBR–[5/6/7]–B HYS72D128320GBR–[5/6/7]–B HYS72D643[00/20]GBR–[5/6/7]–B HYS72D128320GBR–[5/6/7]–B Revision History: Rev. 1.1 Previous Version: Rev. 1.0 Page Subjects (major changes since last revision) 21,22 Registerd and PLL current added We Listen to Your Comments Any information within this document that you feel is ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Low Profile Modules form factor: 128.95 mm 28.58 mm 4.00 mm 133.35 mm 30.48 mm (1.2”) • JEDEC standard reference layout for one rank 256MB and 512MB, two ranks 512MB and 1GByte: PC2700 Registered DIMM Raw Cards A,B,C,D • Gold plated contacts Table 1 Performance Part Number Speed Code Speed Grade Component Module f max ...
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... Example: HYS72D64300GR-5-B, indicating rev. C dies are used for SDRAM components. The “compliance code” is printed on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module ...
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Pin Configuration The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 3 abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 numbering is depicted in Figure ...
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Table 3 Pin Configuration of RDIMM (cont’d) Pin# Name Pin Buffer Function Type Type Data Signals 2 DQ0 I/O SSTL Data Bus 63:0 4 DQ1 I/O SSTL 6 DQ2 I/O SSTL 8 DQ3 I/O SSTL 94 DQ4 I/O SSTL 95 ...
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Table 3 Pin Configuration of RDIMM (cont’d) Pin# Name Pin Buffer Function Type Type 78 DQS6 I/O SSTL Data Strobes 8:0 86 DQS7 I/O SSTL 47 DQS8 I/O SSTL 97 DM0 I SSTL Data Mask 0 Note: 8 based module ...
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Table 3 Pin Configuration of RDIMM (cont’d) Pin# Name Pin Buffer Function Type Type V 3, GND – Ground Plane SS 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, ...
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Standard Height Front View PIN 1 Back View PIN 93 1U Height Front View PIN 1 Back View PIN 93 Figure 1 PCB with Pin Connector Data Sheet HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules PIN 52 PIN 53 PIN ...
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Table 6 Address Format Density Organization Memory Ranks 256 MB 32M 512 MB 64M 72 1 512 MB 64M 128M 72 2 Data Sheet HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules SDRAMs # ...
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RS0 DQS0 DM0/DQS9 CS DM DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 I/O 4 DQ4 I/O 5 DQ5 DQ6 I/O 6 I/O 7 DQ7 DQS1 DM1/DQS10 CS DM I/O 0 DQ8 DQ9 I/O 1 ...
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RS1 RS0 DQS0 DM0/DQS9 DM DQS CS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DM1/DQS10 DM DQS CS DQ8 I/O 0 ...
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VSS RS0B RS0A DQS0 DQS CS DM DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQS1 CS DQS DM I/O 0 DQ8 I/O 1 DQ9 D1 I/O 2 DQ10 I/O 3 DQ11 DQS2 DQS CS ...
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V SS RS1 RS0 DQS0 DQS CS DM I/O 0 DQ0 I/O 1 DQ1 D0 I/O 2 DQ2 I/O 3 DQ3 DQS1 CS DQS DM I/O 0 DQ8 I/O 1 DQ9 D1 I/O 2 DQ10 I/O 3 DQ11 DQS2 DQS ...
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Electrical Characteristics 3.1 Operating Conditions Table 7 Absolute Maximum Ratings Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply relative Voltage on supply relative to ...
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Table 8 Electrical Characteristics and DC Operating Conditions (cont’d) Parameter Symbol Input Leakage Current Output Leakage Current OZ I Output High Current, OH Normal Strength Driver I Output Low OL Current, Normal Strength Driver ...
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Table 9 I Specifications DD 256 MB 512 Rank 1 Rank –5 –5 typ. max. typ. I 1690 1960 2500 DD0 I 1825 2005 2770 DD1 I 698 725 752 DD2P I 1076 1139 1508 DD2F ...
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I Table 10 Specifications DD 256 MB 512 Rank 1Ranks –6 –6 typ. max. typ. I 1495 1720 2260 DD0 I 1630 1810 2530 DD1 I 484 511 538 DD2P I 835 925 1240 DD2F I ...
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I Table 11 Specifications DD 256 MB 512 Rank 1 Rank –7 –7 typ. max. typ. I 1263 1488 1938 DD0 I 1398 1578 2208 DD1 I 426 448 475 DD2P I 691 736 1006 DD2F ...
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AC Characteristics Table 12 AC Timing - Absolute Specifications –5/–6/–7 Parameter Symbol t DQ output access time from AC CK/CK t DQS output access time from DQSCK CK/CK CK high-level width low-level width CL t ...
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Table 12 AC Timing - Absolute Specifications –5/–6/–7 (cont’d) Parameter Symbol t Address and control input IS setup time t Address and control input hold IH time t Read preamble RPRE t Read postamble RPST t Active to Precharge command ...
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The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the ...
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SPD Contents Table 13 SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5 Label Code Jedec SPD Revision Rev 1.0 Byte# Description 0 Programmed SPD Bytes in E2PROM 1 Total number of Bytes in E2PROM 2 Memory Type (DDR = 07h) ...
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Table 13 SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5 Label Code Jedec SPD Revision Rev 1.0 Byte# Description 16 Burst Length Supported 17 Number of Banks on SDRAM Device 18 CAS Latency 19 CS Latency 20 Write Latency 21 DIMM ...
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Table 13 SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5 Label Code Jedec SPD Revision Rev 1.0 Byte# Description 42 tRFCmin [ns] 43 tCKmax [ns] 44 tDQSQmax [ns] 45 tQHSmax [ns] 46 not used 47 DIMM PCB Height ...
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Table 13 SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5 Label Code Jedec SPD Revision Rev 1.0 Byte# Description 75 Part Number, Char 3 76 Part Number, Char 4 77 Part Number, Char 5 78 Part Number, Char 6 79 Part ...
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... HYS72D[32/64/128]3[00/20]GBR SPD Contents 512 MB 256 Ranks 1 Rank PC3200R–30330 PC3200R–30330 Rev 0.0 Rev 0.0 HEX HEX 512 MB 256 Ranks 1 Rank PC2700R– PC2700R– 25330 25330 Rev 0.0 Rev 0.0 HEX HEX Rev. 1.1, 2004-04 10102003-01E2-HPA8 ...
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... SPD Contents 256 Rank PC2700R– 25330 Rev 0.0 HEX Rev. 1.1, 2004-04 10102003-01E2-HPA8 ...
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... SPD Contents 256 Rank PC2700R– 25330 Rev 0.0 HEX Rev. 1.1, 2004-04 10102003-01E2-HPA8 ...
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... SPD Contents 256 Rank PC2700R– 25330 Rev 0.0 HEX Rev. 1.1, 2004-04 10102003-01E2-HPA8 ...
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... SPD Contents 256 Rank PC2700R– 25330 Rev 0.0 HEX Rev. 1.1, 2004-04 10102003-01E2-HPA8 ...
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... HEX SPD Contents 256 Rank PC2700R– 25330 Rev 0.0 HEX Rev. 1.1, 2004-04 10102003-01E2-HPA8 ...
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Table 15 SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in E2PROM 1 Total number of Bytes in E2PROM 2 Memory Type (DDR = 07h) 3 Number of Row Addresses 4 ...
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Table 15 SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B Label Code Jedec SPD Revision Byte# Description 26 tAC SDRAM @ CLmax -1 [ns] 27 tRPmin [ns] 28 tRRDmin [ns] 29 tRCDmin [ns] 30 tRASmin [ns] 31 Module Density per Rank 32 ...
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Table 15 SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B Label Code Jedec SPD Revision Byte# Description 70 JEDEC ID Code of Infineon (7) 71 JEDEC ID Code of Infineon (8) 72 Module Manufacturer Location 73 Part Number, Char 1 74 Part ...
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Table 15 SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B Label Code Jedec SPD Revision Byte# Description 97 Module Serial Number (3) 98 Module Serial Number ( 127 not used Data Sheet HYS72D[32/64/128]3[00/20]GBR Registered Double Data Rate SDRAM Modules 1 ...
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Package Outlines 1 2.5 ±0.1 ø0 64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 6 Package Outlines Raw Card A L-DIM 184-21 Data Sheet Registered Double Data Rate SDRAM ...
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64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 7 Package Outlines Raw Card B L-DIM 184-23 Data Sheet Registered Double Data Rate SDRAM Modules 133.35 128.95 ...
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64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 8 Package Outline Raw Card C L-DIM 184-22 Data Sheet Registered Double Data Rate SDRAM Modules 133.35 128.95 ...
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64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 9 Package Outline Raw card D L-DIM 184-24 Data Sheet Registered Double Data Rate SDRAM Modules 133.35 128.95 ...
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Application Note Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during ...
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Power-Up Sequence with RESET — Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on ...
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SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT). The deactivate time defines the time in which the clocks and the control and address signals must maintain ...
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Self Refresh Exit (RESET low, clocks running) — Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should ...
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Published by Infineon Technologies AG ...