M36P0R9060N0ZANE NUMONYX [Numonyx B.V], M36P0R9060N0ZANE Datasheet
M36P0R9060N0ZANE
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M36P0R9060N0ZANE Summary of contents
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Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 64 Mbit (Burst) PSRAM, 1.8V supply, Mux I/O, Multi-Chip Package Feature summary ■ Multi-Chip Package – 1 die of 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash memory – ...
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Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36P0R9060N0 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36P0R9060N0 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58PRxxxJN and M69KM096AA datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. Recommended operating conditions do not allow more than one memory to be active at the same time ...
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M36P0R9060N0 Table 1. Signal names (1) A16-A24 ADQ0-ADQ15 V DDQ V PPF V DDF V CCP WAIT NC DU Flash Memory DPD F PSRAM E P ...
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Summary description Figure 2. TFBGA connections (top view through package DDQ 8/23 ...
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... Flash memory. 2.4 Clock (K) The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KM096AA for the PSRAM and M58PRxxxJN for the Flash memory. and Table 1., Signal ...
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Signal descriptions 2.5 Wait (WAIT) WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of ...
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M36P0R9060N0 2.11 PSRAM Chip Enable input (E The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (V ), the device is disabled, and goes automatically in low-power Standby mode or Deep IH Power-down mode, according to ...
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Signal descriptions 2.17 Deep Power-Down input (DPD The Deep Power-Down input is used to put the device in a Deep Power-Down mode. When the device is in Standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting ...
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M36P0R9060N0 2.22 V Ground the common ground reference for all voltage measurements in the Flashmemory SS (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in ...
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Functional description 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: E and E for the PSRAM. P Recommended operating conditions do ...
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M36P0R9060N0 Table 2. Main operating modes (2) Operation Bus Read Bus Write Address Latch Output Disable Standby ...
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Maximum rating 4 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any ...
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M36P0R9060N0 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the ...
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... V means V DD DDF Table 5. Capacitance Symbol C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested. Please refer to the M58PRxxxJN and M69KM096AA datasheets for further DC and AC characteristics values and illustrations. 18/23 DEVICE UNDER TEST CCP (1) Parameter Test Condition ...
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M36P0R9060N0 6 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...
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Package mechanical Table 6. Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package data Symbol ddd 20/23 millimeters Typ Min Max 1.20 0.20 0.85 0.35 ...
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M36P0R9060N0 7 Part numbering Table 7. Ordering information scheme Example: Device Type M36 = Multi-Chip Package (Flash + PSRAM) Flash 1 Architecture P = Multi-Level, Multiple Bank, Large Buffer Flash 2 Architecture Die Operating Voltage R = ...
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Revision history 8 Revision history Table 8. Document revision history Date 21-Jul-2006 30-Nov-2007 22/23 Revision 0.1 Initial release. 0.2 Applied Numonyx branding. M36P0R9060N0 Changes ...
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M36P0R9060N0 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF ...