ZL50233GDC ZARLINK [Zarlink Semiconductor Inc], ZL50233GDC Datasheet - Page 29

• Manufacturer Part Number: ZL50233GDC
• Description: 4 Channel Voice Echo Cancellor
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Data Sheet
Bit 7
Unused
Unused
MTDBI
MTDAI
Format
PWUP
Unused
Unused
I<4:0>
Law
Bit 7
IRQ
IRQ
Bit 6
Unused
Unused Bits.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711)
PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM
code
A/ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, select -Law companded
PCM code
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo cancellers A and B execute their initialization routine which presets their registers, Base
Address+00
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their specific
application.
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is
read. Logic Low indicates that no interrupt is pending and the FIFO is empty.
Unused bit.
Unused bit.
I<4:0> binary code indicates the channel number at which a Tone Detector state change has
occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Unused
.
Bit 6
Power-up 00
Main Control Register 1 (EC Group 1)
.
hex
Bit 5
Unused
to Base Address+3F
Unused
Bit 5
hex
Power-up 00
Functional Description of Register Bits
Functional Description of Register Bits
Bit 4
MTDBI
Interrupt FIFO Register
Zarlink Semiconductor Inc.
Bit 4
hex
I4
hex
, to default Reset Value and clears the Adaptive Filter
Bit 3
MTDAI
Bit 3
I3
Bit 2
Format
R/W Address: 410
Bit 2
I2
R/W Address: 401
Bit 1
Law
Bit 1
I1
hex
Bit 0
PWUP
ZL50233
Bit 0
hex
I0
29