ZL50233GDC ZARLINK [Zarlink Semiconductor Inc], ZL50233GDC Datasheet - Page 18

• Manufacturer Part Number: ZL50233GDC
• Description: 4 Channel Voice Echo Cancellor
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address
mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the ZL50233. To provide more flexibility, the
MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<3:0> allow Tone Disable to be masked or
unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section.
7.0
The ZL50233 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
7.1
The TAP provides access to many test functions of the ZL50233. It consists of four input pins and one output pin.
The following pins are found on the TAP.
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7.2
In accordance with the IEEE 1149.1 standard, the ZL50233 uses public instructions. The JTAG Interface contains a
3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to
select the test data register that will operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register scanning.
ZL50233
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrent with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
V
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to V
DD1
Test Access Port (TAP)
Instruction Register
JTAG Support
when it is not driven from an external source.
DD1
when it is not driven from an external source.
Zarlink Semiconductor Inc.
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Data Sheet