ZL30409/DDA ZARLINK [Zarlink Semiconductor Inc], ZL30409/DDA Datasheet - Page 8

• Manufacturer Part Number: ZL30409/DDA
• Description: T1/E1 System Synchronizer with Stratum 3 Holdover
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock outputs
are locked to one another for all operating states, and are also locked to the selected input reference in Normal
Mode. See Figures 14 & 16.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover)
when the frequency of the incoming signal is outside the Auto-Holdover capture range. (See AC Electrical
Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the
incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output
signal locked to the input signal. The holdover output signal in the ZL30409 is based on the incoming signal 30ms
minimum to 60ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible
because the Holdover Mode is very accurate (e.g.,
and output after switching back to Normal Mode is preserved.
State Machine Control
As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit and the
DPLL. Control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). When
switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and
disabled when PCCi = 0.
Figure 5 - Output Interface Circuit Block Diagram
DPLL
From
Tapped
Tapped
Tapped
Tapped
Delay
Delay
Delay
Delay
Line
Line
Line
Line
Zarlink Semiconductor Inc.
ZL30409
±
0.05ppm).
12MHz
16MHz
12MHz
19MHz
8
DS2 Divider
T1 Divider
E1 Divider
Consequently, the phase delay between the input
C19o
RSP
TSP
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
C6o
Data Sheet