ZL30131GGG ZARLINK [Zarlink Semiconductor Inc], ZL30131GGG Datasheet - Page 3

• Manufacturer Part Number: ZL30131GGG
• Description: OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Control
Status
Pin #
K10
J10
H5
C2
D2
D3
H1
E1
K1
J7
J5
J1
mode_0
mode_1
diff0_en
diff1_en
p1_clk0
p1_clk1
ref_out
p0_fp1
Name
hs_en
rst_b
hold
lock
Type
I/O
O
O
O
O
I
I
I
I
O
O
I
u
u
u
u
Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz
Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in
addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).
Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p1_clk0
frequency within the range of 2 kHz to 100 MHz. The default frequency for this
output is 3.088 MHz (2x DS1).
Rx DPLL Selected Output Reference (LVCMOS). This is a buffered copy of the
output of the reference selector for the Rx DPLL. Switching between input
reference clocks at this output is not hitless.
Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
Tx DPLL Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high
at this input enables hitless reference switching. A logic low disables hitless
reference switching and re-aligns the Tx DPLL’s output phase to the phase of the
selected reference input. This feature can also be controlled through software
registers. This pin is internally pulled up to Vdd.
Tx DPLL Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels
on these pins determine the default mode of operation for the Tx DPLL
(Automatic, Normal, Holdover or Freerun). After reset, the mode of operation can
be controlled directly with these pins, or by accessing the tx_dpll_modesel
register (0x1F) through the serial interface. This pin is internally pulled up to Vdd.
Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 0 driver is enabled. When set low, the differential
driver is tristated reducing power consumption. This pin is internally pulled up to
Vdd.
Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 1 driver is enabled. When set low, the differential
driver is tristated reducing power consumption.This pin is internally pulled up to
Vdd.
Lock Indicator (LVCMOS). This is the lock indicator pin for the Tx DPLL. This
output goes high when the Tx DPLL’s output is frequency and phase locked to
the input reference.
Holdover Indicator (LVCMOS). This pin goes high when the Tx DPLL enters the
holdover mode.
Zarlink Semiconductor Inc.
ZL30131
6
Description
Short Form Data Sheet