ML2264CCR MICRO-LINEAR [Micro Linear Corporation], ML2264CCR Datasheet - Page 13

• Manufacturer Part Number: ML2264CCR
• Description: 4-Channel High-Speed 8-Bit A/D Converter with T/H (S/H)
• Manufacturer: MICRO-LINEAR [Micro Linear Corporation]

where V
V
harmonics.
1.6.2 Signal-To-Noise Ratio
Signal-to-noise ratio (SNR) is the measured signal to noise
at the output of the converter. The signal is the rms
magnitude of the fundamental. Noise is the rms sum of all
the nonfundamental signals up to half the sampling
frequency. SNR is dependent on the number of
quantization levels used in the digitization process; the
more the levels, the smaller the quantization noise. The
theoretical SNR for a sine wave is given by
SNR = (6.02N + 1.76) dB
where N is the number of bits. Thus for ideal 8-bit
converter, SNR = 49.92 dB.
1.6.3 HARMONIC DISTORTION
Harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. Total harmonic distortion
(THD) of the ML2264 is defined as
where V
V
harmonics.
1.6.4 Intermodulation Distortion
With inputs consisting of sine waves at two frequencies,
f
distortion products, of order (m + n), at sum and
difference frequencies of mf
3 … Intermodulation terms are those for which m or n is
not equal to zero. The (IMD) intermodulation distortion
specification includes the second order terms (f
f
(f
1.7 DIGITAL INTERFACE
The ML2264 has two basic interface modes, RD and WR-
RD, which are selected by the MODE input pin.
1.7.1 RD Mode
In the RD mode, WR/RDY pin is configured as the RDY
output. The read mode performs a conversion with a
single RD pulse. This allows the µP to start a conversion,
wait, and then read data with a single read instruction.
The timing for the RD mode is shown in Figure 4. To do a
conversion, CS must be low to select the device. After CS
goes low, the RDY output goes low indicating that the
device is ready to do a conversion. The conversion starts
A
A
A
2
2
and f
– f
, V
, V
+ 2f
B
3
3
) and the third order terms (2f
, V
, V
B
B
), and (f
1
1
, any active device with nonlinearities will create
4
4
is the rms amplitude of the fundamental and
is the rms amplitude of the fundamental and
, V
, V
5
5
20
20
are the rms amplitudes of the individual
are the rms amplitudes of the individual
A
log
log
– 2f
(
(
V
V
B
2
2
) only.
2
2
V
V
A
3
3
2
2
+ nf
V
V
V
V
1
1
B
4
4
2
2
, where m, n = 0, 1, 2,
A
+ f
V
V
5
5
B
2 1 2
2 1 2
), (2f
)
)
A
A
– f
+ f
B
),
B
) and
on the falling edge of RD. While RD is low, the MSB and
LSB decisions are made with internally generated clock
edges. When the conversion is complete, RDY goes high
and INT goes low signaling the end of the conversion.
After INT goes low, the data outputs go from high
impedance to active state with valid output data. Data
stays valid until either RD or CS goes high. When either
signal goes high, the output data lines return to the high
impedance state and INT returns high.
1.7.2 WR-RD Mode
In the WR-RD mode, the WR/RDY pin is configured as the
WR input. In this mode, WR initiates the conversion and
RD controls reading the output data. This can be done in
several ways, described below.
1.7.3 WR-RD Mode — Using Internal Delay
(t
The timing is shown in Figure 5. To do a conversion, CS
must be low to select the device. Then, WR falling edge
triggers the conversion. While WR is low, the MSB
comparison is made. When WR returns high the LSB
decision is made. After some internal delay, INT goes low
indicating end of conversion. Valid data will appear on
DB0–7 when RD is pulled low. INT is then reset by the
rising edge of either CS or RD.
1.7.4 WR-RD Mode — Reading Before Delay
(t
The internally generated delay for the LSB decision when
t
tolerances of t
will result without loss of accuracy by bringing RD low
within the minimum time specified for t
diagram for this mode is shown in Figure 6. WR is the
same as when t
low t
low indicating an end of conversion after the falling edge
of RD and is reset on the rising edge of RD or CS. When
RD is brought low before INT goes low the data bus
always remains in the high-impedance state until INT .
1.7.5 WR-RD Mode — Stand Alone Operation
Stand alone operation can be implemented by tying CS
and RD low as shown in Figure 7. WR initiates a
conversion as before. When WR is low, the MSB
comparison is made. When, WR goes high, the LSB
comparison is made. Since RD is already low, the output
data will appear automatically at end of conversion. Since
RD is always low, INT is reset on rising edge of WR and
goes low at end of conversion.
1.7.6 Power-On Reset
When power is first applied, an internal power-on reset
and timer circuit inhibits the CS input and resets the
internal circuitry to prevent the ML2264 from starting in
an unknown state. During this period of approximately
3µs, INT remains high and the data bus is in the high-
impedance state.
RD
RD
RD
> t
> t
< t
RD
INTL
INTL
INTL
ns after WR rising edge and before INT. INT goes
is longer than necessary due to circuit design
)
)
INTL
RD
delay. If desired, a faster conversion
> t
INTL
. But in this case, RD is brought
RD
. The timing
ML2264
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