ML2264CCR MICRO-LINEAR [Micro Linear Corporation], ML2264CCR Datasheet - Page 10

• Manufacturer Part Number: ML2264CCR
• Description: 4-Channel High-Speed 8-Bit A/D Converter with T/H (S/H)
• Manufacturer: MICRO-LINEAR [Micro Linear Corporation]

ML2264
the MSB comparators will be tracking it as long as the
slew rate of the analog input is slow enough so that the
MSB comparators can respond. The ML2264 can track
and hold signals with slew rates as high as 0.25V/µs
(16kHz @ 5 volts) without sacrificing conversion
accuracy.
The ML2264 in S/H mode does not have the slew rate
limitation of the T/H mode since an internal sample and
hold acquires the analog signal, holds it internally, and
then performs a conversion. Since this is a true sample
and hold function, the S/H mode can theoretically digitize
signals of frequencies much higher than the T/H mode.
The ML2264 in S/H mode can digitize signals of
frequencies as high as 250kHz @ 5V (slew rates as high as
4V/µs) without sacrificing conversion accuracy. In most
applications, the S/H mode is more desirable than T/H
mode because of the better dynamic performance.
1.3.1 Converter — T/H Mode
The operating sequence for the WR-RD mode is illustrated
in Figure 9a. Initially, the internal comparators are auto-
zeroed while WR is high. A conversion is initiated by the
falling edge of WR. While WR is low, the MSB
comparators are tracking the analog input and comparing
this voltage against voltages from the internal resistor
ladder. At the same time, the input is being acquired or
sampled by LSB comparators. On the rising edge of WR,
the MSB comparator results are latched, and the LSB
acquisition time is ended by closing the sampling switch
to the LSB comparators. While WR is high, the LSB
comparators then compare the residual input voltage
against internal voltages from the resistor ladder to
determine the 4 LSB’s. When the LSB comparison or
conversion is complete, INT goes low and latches the
conversion result into the output latches. Then, the
comparators are auto-zeroed while WR is high before
another conversion can start.
The operating sequence for RD mode, is similar to that
described above for the WR-RD mode, except the
conversion is initiated by the falling edge of RD, and the
MSB and LSB conversions are generated by internal clock
edges that are generated while RD is low.
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1.3.2 Converter — S/H Mode
The operating sequence for S/H mode is illustrated in
Figure 9b. Notice that it is similar to T/H mode described
above except this mode has a true sample and hold
function. The falling edge of INT closes the sampling
switch and starts the acquisition period where the analog
input is sampled at the same time all comparators are
auto-zeroed. The falling edge of WR opens the internal
sampling switch, ends the acquisition period, and starts
the conversion on the internally sample and held signal.
The MSB comparators make their decisions while WR is
low. On the rising edge of WR, the MSB comparator
results are latched. The LSB comparators make their
decision when WR is high. When the LSB comparison or
conversion is complete, INT goes low and latches the
conversion result into the output buffers. Then, the
acquisition period begins again and the converter is ready
for the next conversion.
The operating sequence for the RD mode is the same as
the WR-RD mode, except the conversion is initiated by
the falling edge of RD, and the MSB and LSB conversions
are generated by internal clock edges that are generated
while RD is low.
V
IN
Figure 8. Converter Equivalent Input Circuit
R
S
LADDER
LADDER
11pF
TO MS
TO LS
R
R
6.4K
4K
16 MSB COMPARATORS
ON
ON
15 LSB COMPARATORS
S1
S2
S4
S5
1.34pF
0.65pF
1pF
1pF
1pF
1.2K
R
3.6K
R
ON
ON
S6
S3