AK4122A AKM [Asahi Kasei Microsystems], AK4122A Datasheet
AK4122A
Related parts for AK4122A
AK4122A Summary of contents
Page 1
... AK4122A, the system can take very simple configuration because the AK4122A has an internal PLL and does not need any master clock at slave mode. Then the AK4122A is suitable for the application interfacing to different sample rates like Car Audio, DVD recorder, etc. ...
Page 2
... Audio SDTIO I/F SDTIO MCLK2 AVDD AVSS MS1076-E-01 INT0 INT1 OPS1-0 DIR De-em SRC Filter ISEL1-0 PLL Control Register DVDD DVSS CDTO CDTI CCLK CSN Block diagram - 2 - [AK4122A] INT2 R FILT TX PORT3 LRCK Serial OSEL BICK Audio SDTO I/F BYPS TX PDN SMUTE LRCK BICK SDTO ...
Page 3
... Ordering Guide −10 ∼ +70°C AK4122AVQ AKD4122A Evaluation Board for AK4122A ■ Pin Layout INT0 37 INT1 SDTO 40 BICK 41 LRCK 42 OMCLK 43 DVSS 44 DVDD 45 BVSS 46 CSN 47 CCLK 48 MS1076-E-01 48pin LQFP (0.5mm pitch AK4122AVQ Top View ...
Page 4
... This pin should be connected to AVSS. Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 9 Pin This pin should be connected to AVSS. Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin) Test 10 Pin This pin should be connected to AVSS. Test 11 Pin - 4 - Function [AK4122A] 2010/05 ...
Page 5
... Audio Serial Data Output Pin Audio Serial Data Clock Pin Output Channel Clock Pin Master Clock Input Pin Digital Ground Pin Digital Power Supply Pin, 3.0 ∼ 3.6V Substrate Ground Pin This pin should be connected to AVSS. Chip Select Pin Control Data Clock Pin - 5 - [AK4122A] 2010/05 ...
Page 6
... This pin should be connected to DVDD or DVSS. These pins should be open. These pins should be open. These pins should be connected to DVSS. This pin should be open. This pin should be connected to DVSS. These pins should be open. This pin should be connected to DVSS. These pins should be connected to AVSS [AK4122A] 2010/05 ...
Page 7
... WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1076-E-01 ABSOLUTE MAXIMUM RATINGS Symbol min −0.3 AVDD −0.3 DVDD ΔGND (Note 2) IIN −0.3 VIND1 −0.3 VIND2 −10 Ta −65 Tstg Symbol min AVDD 3.0 DVDD 3 [AK4122A] max 4.6 4.6 - 0.3 ±10 - DVDD+0.3 AVDD+0.3 70 150 typ max 3.3 3.6 3.3 AVDD Units °C °C Units ...
Page 8
... FSO/FSI = 44.1kHz/48kHz Ratio between Input and Output Sample Rate Note 4. Input data for SRC corresponds to 24bit data. When LSB 4bit data is input, the AK4122A calculates the data as “0” because SRC is 20bit calculation. Therefore, SRC outputs “0” data. Note 5. Measured by ROHDE & SCHWARZ UPD04, Rejection Filter = wide, 8192point FFT. ...
Page 9
... Units kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB 1/fs Units μA Units μA 2010/05 ...
Page 10
... S mode) tLRS tBSD - 10 - [AK4122A] typ max Units 36.864 MHz kHz kHz kHz ...
Page 11
... PDN Pulse Width Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. In case of using INT2. When INT2 is not used, the max value is not limited. Note 13. The AK4122A can be reset by bringing the PDN pin = “L”. MS1076-E-01 Symbol ...
Page 12
... SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as output port. MS1076-E-01 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Clock Timing tLRB tBSD tSDS tSDH Audio Interface Timing (Slave mode [AK4122A] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL 2010/05 ...
Page 13
... SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as output port. CSN CCLK CDTI CDTO MS1076-E-01 tBSD tSDS tSDH Audio Interface Timing (Master mode) tCSS tCCKL tCDS C1 C0 Hi-Z WRITE/READ Command Input Timing - 13 - [AK4122A] 50%DVDD dBCK 50%DVDD 50%DVDD VIH VIL VIH VIL tCCKH VIH VIL tCDH VIH R/W VIL 2010/05 ...
Page 14
... CSN CCLK CDTI D2 CDTO CSN CCLK CDTI A1 CDTO MS1076-E- Hi-Z WRITE Data Input Timing A0 tDCD Hi-Z READ Data Output Timing [AK4122A] tCSW VIH VIL tCSH VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL D7 D6 50%DVDD 2010/05 ...
Page 15
... CSN CCLK CDTI CDTO D2 PDN MS1076-E-01 tCSW tCSH D1 D0 READ Data Output Timing 2 tPD Power Down & Reset Timing - 15 - [AK4122A] VIH VIL VIH VIL VIH VIL tCCZ Hi-Z 50%DVDD VIL 2010/05 ...
Page 16
... PORT2 → SRC → PORT3 DIR → SRC → PORT3 PORT1 → PORT3 PORT2 → PORT3 DIR → PORT3 PORT1 → SRC → PORT2 DIR → SRC → PORT2 PORT1 → PORT2 DIR → PORT2 2 S Compatible) when the DIR is [AK4122A] Table 1. 2010/05 ...
Page 17
... MCLK frequency when PORT2 and PORT3 are master mode. In MCLK2 32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz 0 256fs 1 384fs 0 512fs 1 768fs OMCLK 32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz 0 256fs 1 384fs 0 512fs 1 768fs - 17 - [AK4122A] Setting Setting 256fs 384fs (default) N/A N/A 256fs 384fs (default) N/A N/A 2010/05 ...
Page 18
... MCLK should be supplied to the port which is in master mode, and the AK4122A outputs BICK and LRCK. BICK and LRCK should be supplied externally to the port which is in slave mode, and MCLK is not needed fro this ports. When PORT2 is used as an input port, the M/S2 pin should be set “H” or “ ...
Page 19
... Don't Care 23 22 Lch Data Figure 4. Mode 2 Timing Don't Care Lch Data Figure 5. Mode 3 Timing - 19 - [AK4122A Rch Data ...
Page 20
... Figure 6. Mode 0 Timing Don't Care 23 22 Lch Data Figure 7. Mode 1 Timing - 20 - [AK4122A] (Table 9). In all modes, the serial data is LRCK BICK ≥ 32fs H/L ≥ 48fs (default) H/L ≥ 48fs L/H ≥ 48fs H ...
Page 21
... Lch Data Figure 10. Mode 0 Timing Lch Data Figure 11. Mode 1 Timing - 21 - [AK4122A Don't Care Rch Data ...
Page 22
... (1) The output data is attenuated by −∞ during 1024 LRCK cycles (1024/fs). (2) If the soft mute is cancelled before attenuating to −∞, the attenuation is discontinued and returned to 0dB in the same clock cycles. MS1076-E- Figure 12. Soft Mute Function - 22 - [AK4122A 2010/05 ...
Page 23
... System Reset and Power-Down The AK4122A has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down mode activated by the PWN bit. The AK4122A should be reset once at power-up by bringing the PDN pin = “L”. PDN pin: All analog and digital circuits are placed in power-down and reset modes by bringing the PDN pin = “L”. All the registers are initialized and clocks are stopped. Read/Write operations to the registers are disabled. PWN bit (Address 00H ...
Page 24
... Bringing the PDN pin = “L” sets the AK4122A in power-down mode and initializes digital filters. When the PDN pin = “L”, the SDTO output is “L”. The AK4122A should be reset once by bringing the PDN pin = “L” upon power-up. The SDTO becomes valid in less than 100ms from the rising edge of PDN after a reset release by clock supply. Until the SDTO becomes valid, it outputs “ ...
Page 25
... The AK4122A can output through data from the digital receiver inputs (RX1-4) to the TX pin. The OPS1-0 bits can select the source of the TX pin output. TX output can be stopped by TXE bit. The AK4122A does not have a TX output buffer (Line Driver), therefore the TX pin cannot drive the 75Ω coaxial cable directly. ...
Page 26
... Note 19. Coaxial input only : if a coupling level to this input by the next RX input line pattern exceeds 50mV, an malfunction may occur. In this case possible to lower the coupling level by adding this decoupling capacitor. Note 20. Ground of the RCA connector and terminator should be connected to AVSS of the AK4122A with low impedance on PC board. Optical ...
Page 27
... Sampling Frequency and Pre-emphasis Detection for DIR The AK4122A has two methods for detecting sampling frequency for DIR. The sampling frequency is detected by comparing the recovered clock to the MCLK2 or OMCLK frequency, and the detected frequency is reported on FS3-0 bits. XTL1-0 bits , ICKS1-0 bits and OCKS1-0 bits must be set according to the FSO and MCLK frequencies for the detection ...
Page 28
... When the AK4122A loses lock, the channel status bits are initialized. In this initial state, the INT0 and INT2 pins output an OR’ed signal between UNLCK and PAR bits. The INT1 pin outputs an OR’ed signal between AUTO, V and AUDN. ...
Page 29
... V, AUDN) SDTIO / SDTO (PAR error) Figure 17. INT2-0 Timing (UNLCK, PAR, AUTO, V, AUDN bits) MS1076-E-01 Hold Time = 0 “0” Hold “1” Free Run fs : around 20kHz Mute “L” Output Previous Data - 29 - [AK4122A] Hold Time (max:4096/fs) “0” : Normal Operation 2010/05 ...
Page 30
... INT2 pin Register 07H Read 07H BICK, LRCK SDTIO / SDTO Figure 18. INT2-0 Timing (STC, CINT, QINT bits) (1) Hold Time : max. 4096/fs (2) Hold Time = 0 MS1076-E-01 (1) (2) “0” Hold “1” “0” [AK4122A] (1) (2) Hold “1” “0” : Normal Operation 2010/05 ...
Page 31
... INT1 pin INT2 pin Register 08H Read 08H BICK, LRCK SDTIO / SDTO (1) Hold Time: max. 4096/fs (2) Hold Time = 0 MS1076-E-01 (1) (2) “0” Hold “1” “0” Figure 19. INT2-0 Timing (DAT bit [AK4122A] (1) (2) Hold “1” “0” : Normal Operation 2010/05 ...
Page 32
... Figure 20. Interrupt Handling Sequence Example 1 MS1076-E-01 PD pin ="L" to "H" Read 07H, 08H INT0/1 pin ="H" Yes Mute SDTIO / SDTO Read 07H, 08H (Each Error Handling) Read 07H, 08H (Resets registers) No INT0/1 pin ="H" Yes - 32 - [AK4122A] Initialize No 2010/05 ...
Page 33
... Figure 21. Interrupt Handling Sequence Example 2 MS1076-E-01 PD pin ="L" to "H" Initialize Read 07H No INT1 pin ="H" Yes Read 07H and Detect QSUB= “1” (Read Q-buffer) No QCRC = “0” Yes No INT1 pin ="L" Yes New data is valid - 33 - [AK4122A] New data is invalid 2010/05 ...
Page 34
... Q-subcode buffers The DIR of the AK4122A has a Q-subcode buffer for CD applications. The AK4122A takes Q-subcode into registers under the following conditions: 1) The sync word (S0, S1) consists of at least 16 “0”s. 2) The start bit is “1”. 3) Those 7-bits Q-W follow the start bit. ...
Page 35
... DTS-CD bitstream, the DTSCD bit goes to “1”. If the next sync code does not occur within 4096 frames, the DTSCD bit returns to “0” until either the AK4122A detects the stream again. OR’ed value of the NPCM and DTSCD bits are output to the AUTO bit ...
Page 36
... Q35 Q46 Q45 Q44 Q43 Q54 Q53 Q52 Q51 Q62 Q61 Q60 Q59 Q70 Q69 Q68 Q67 Q78 Q77 Q76 Q75 [AK4122A] D0 PWN OCKS0 DIF0 OPS0 MQIT0 MQIT1 MDAT0 QINT FS0 QCRC CR0 CR8 CR16 CR24 CR32 PC0 PC8 PD0 PD8 ...
Page 37
... When SMUTE bit = “1”, SDTO and SDTIO outputs “L”. TXE: TX Output enable 0: Disable, TX outputs “L”. 1: Enable (default) XTL1-0: Reference MCLK Frequency Select Initial values are “11”. MS1076-E- XTL1 XTL0 TXE SMUTE R/W R/W R/W R 12, Table 13) (Table 16 DEAU DEM1 DEM0 R/W R/W R [AK4122A] D0 PWN R/W 1 2010/05 ...
Page 38
... Initial values are “00”. OSEL: Output Port Select Initial values are “0”. BYPS: Select Bypass mode 0: SRC mode (default) 1: Bypass mode When BYPS bit = “1”, the AK4122A outputs the clocks (BICK, LRCK) and data that is input by input port without SRC. MS1076-E- ...
Page 39
... DIR’s LRCK, the hold time scales with 1/fs. AMUTE: Auto Mute Control 0: Normal operation 1: Auto Mute (default) When AMUTE bit = “1”, SDTIO and SDTO are muted automatically if the AK4122A detects unlock, Non-Audio or Non-PCM/DTS-CD. CS12: Channel Status select 0: Channel 1 (default) 1: Channel 2 These bit selects the channel status for C-bit, AuDN, PEM, FS3-0, Pc, Pd and CRC bit ...
Page 40
... MULK0: Mask enable for UNLCK bit 0: Mask disable (default) 1: Mask enable Registers which the corresponding mask bit is set to “0” affects INT0 and INT2 pins operation. MS1076-E- MULK0 MPAR0 MAUT0 R/W R/W R MV0 MAUD0 MSTC0 MCIT0 R/W R/W R/W R [AK4122A] D0 MQIT0 R 2010/05 ...
Page 41
... MULK1: Mask enable for UNLCK bit 0: Mask disable 1: Mask enable (default) Registers which the corresponding mask bit is set to “0” affects the INT1 pin operation. MS1076-E- MULK1 MPAR1 MAUT1 R/W R/W R MV1 MAUD1 MSTC1 MCIT1 R/W R/W R/W R [AK4122A] D0 MQIT1 R 2010/05 ...
Page 42
... If this mask bit is set to “0”, DAT bit affects the INT1 pin operation. DTS14: DTS-CD 14bit Sync Word Detect 0: No detect 1: Detect (default) DTS16: DST-CD 16bit Sync Word Detect 0: No detect 1: Detect (default) MS1076-E- [AK4122A DTS16 DTS14 MDAT1 MDAT0 R/W R/W R/W R 2010/05 1 ...
Page 43
... This bit goes to “1” parity error or biphase error is detected in the sub-frame. UNLCK: PLL Lock Status 0: Lock 1: Unlock QINT, CINT and STC bits are initialized when 07H is read. MS1076-E- UNLCK PAR AUTO AUDN STC CINT [AK4122A] D0 QINT RD 0 2010/05 ...
Page 44
... This bit is enabled only in professional mode and only for the channel selected by the CS12 bit. MS1076-E- DAT DTSCD NPCM PEM (Table 17) 18 FS3 FS2 FS1 CCRC [AK4122A] D0 FS0 QCRC RD 0 2010/05 ...
Page 45
... Q46 Q45 Q44 Q43 Q54 Q53 Q52 Q51 Q62 Q61 Q60 Q59 Q70 Q69 Q68 Q67 Q78 Q77 Q76 Q75 RD Not initialized [AK4122A] D0 CR0 CR8 CR16 CR24 CR32 D0 PC0 PC8 PD0 PD8 D0 Q2 Q10 Q18 Q26 Q34 Q42 Q50 Q58 Q66 ...
Page 46
... Aux. LSB 16 bits of bitstream 0 Burst_payload repetition time of the burst Figure 26. Data Structure of IEC60958 Contents sync word 1 sync word 2 Burst info Length code Table 22. Burst Preamble Word - 46 - [AK4122A MSB stuffing Value 0xF872 0x4E1F see Table 23 numbers of bits 2010/05 ...
Page 47
... MS1076-E-01 Table 23. Field of Burst Information [AK4122A] Repetition time of burst in IEC60958 frames ≤ 4096 1536 384 1152 1152 1024 384 1152 512 ...
Page 48
... Repetition time Figure 27. Timing example 1 <20mS (Lock time) Stop 2~3 Syncs (B Figure 28. Timing example >4096 frames INT0 hold time Pa Pb <Repetition time Pd 1 [AK4122A 2010/05 ...
Page 49
... Analog Supply 3.0 ~ 3.6V Note: - AVSS, BVSS and DVSS of the AK4122A should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins should not be left floating. MS1076-E-01 SYSTEM DESIGN Digital Supply 3.0 ~ 3.6V DSP3 10μ ...
Page 50
... The AK4122A requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS of the AK4122A must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board ...
Page 51
... Jitter Tolerance Figure 32 shows the jitter tolerance to ILRCK. The jitter frequency and the jitter amplitude shown in jitter quantity. When the jitter amplitude is 0.01Uipp or less, the AK4122A operate normally regardless of the jitter frequency. 10.00 1.00 (2) 0.10 0.01 0.00 1 (1) Normal operation (2) There is a possibility that the distortion degrades. (It may degrade up to about −50dB.) (3) There is a possibility that the output data is lost ...
Page 52
... LQFP(Unit: mm 0.22 ± 0.08 0.5 ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS1076-E-01 PACKAGE 9.0 ± 0.2 7 0.10 M 0° ∼ 10° 0.5 ± 0.2 0.10 Epoxy Cu Solder (Pb free) plate - 52 - [AK4122A] 1.70Max 0.13 ± 0.13 1.40 ± 0.05 0.16 ± 0.07 2010/05 ...
Page 53
... Date (YY/MM/DD) Revision 09/05/19 00 10/05/17 01 MS1076-E-01 MARKING AKM AK4122AVQ XXXXXXX 1 XXXXXXXX: Date code identifier REVISION HISTORY Reason Page Contents First Edition Description ■ Sequence of changing clocks 24 Addition Description is added in notes [AK4122A] 2010/05 ...
Page 54
... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1076-E-01 IMPORTANT NOTICE , and AKM assumes no responsibility for such use, except for the use Note2 [AK4122A] in any safety, life support, or Note1) 2010/05 ...