74F673APC Fairchild Semiconductor, 74F673APC Datasheet - Page 2

• Manufacturer Part Number: 74F673APC
• Description: IC REGISTER SHIFT 16BIT 24-DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F673APC

• Logic Type: Shift Register
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 16
• Function: Serial to Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74F673

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Unit Loading/Fan Out
Functional Description
The 16-bit shift register operates in one of four modes, as
indicated in the Shift Register Operations Table. A HIGH
signal on the Chip Select (CS) input prevents clocking and
forces the Serial Input/Output (SI/O) 3-STATE buffer into
the high impedance state. During serial shift-out opera-
tions, the SI/O buffer is active (i.e., enabled) and the output
data is also recirculated back into the shift register. When
Shift Register Operations Table

H
X
L
CS R/W SHCP STCP
H
L
L
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
HIGH-to-LOW Transition
Control Inputs
H
H
X
L
CS
SHCP
STMR
STCP
R/W
SI/O
Q
0
Pin Names
–Q


X
15
X
X
H
L
High Z
Data In
Data Out Serial Output
Active
Chip Select Input (Active LOW)
Shift Clock Pulse Input (Active Falling Edge)
Store Master Reset Input (Active LOW)
Store Clock Pulse Input
Read/Write Input
Serial Data Input or
3-STATE Serial Output
Parallel Data Outputs
Status
SI/O
Hold
Serial Load
with Recirculation
Parallel Load;
No Shifting
Operating Mode
Description
2
parallel loading the shift register from the storage register,
serial shifting is inhibited.
The storage register has an asynchronous master reset
(STMR) input that overrides all other inputs and forces the
Q
mode when either CS or the Read/Write (R/W) input is
HIGH. With CS and R/W both LOW, the storage register is
parallel loaded from the shift register.
Storage Register Operations Table

H
X
L
0
–Q
STMR
LOW Voltage Level
HIGH Voltage Level
Immaterial
LOW-to-HIGH Transition
15
H
H
H
L
outputs LOW. The storage register is in the Hold
Control Inputs
CS
X
H
X
L
HIGH/LOW
50/33.3
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
3.5/1.0
150/40
U.L.
R/W
X
X
H
L
STCP

X
X
X
Output I
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
70 A/ 0.6 mA
Input I
3 mA/24 mA
1 mA/20 mA
Reset; Outputs LOW
Hold
Hold
Parallel Load
Operating
IH
OH
/I
Mode
/I
IL
OL