LC8904 Sanyo, LC8904 Datasheet - Page 13

• Manufacturer Part Number: LC8904
• Description: Digital Audio Interface Receiver
• Manufacturer: Sanyo

The microprocessor interface controls the following settings and outputs.
1. System stop
2. Data input pin settings
3. Validity flag (V flag) output selection
4. Analog source mode setting
5. Output data format setting
6. Channel status (32 bits) output
7. Output of the 80-bit subcode Q data with CRC flags.
• CCB/SUB pin
• Data I/O address
• Input
• Input code settings
The CCB/SUB pin selects one of two formats. The clocks and codes must be set up appropriately for each of these
formats. SRDT is the output pin when CCB/SUB is low. SRDT goes to the high-impedance state when the
CCB/SUB pin is high, during writes, and when an address for a different output is latched. In contrast with the
SRT pin, the DO pin is a high-level open drain output that functions as the output pin when CCB/SUB is high.
Address are allocated according to the differing formats as listed below.
The DIN1 to DIN4 data input pins have built-in amplifiers, and can accept signals with amplitudes of about
400 Vp-p. Note that the DOUT pin can be set up to output the EIAJ format data by microprocessor interface
commands. (It can also be used to output the V flag.)
System stop by stopping both the VCO and crystal oscillators (DI4)
Selection of data to demodulate (DI5, DI6)
Input data (EIAJ format) output selection
I/O
Data input
Data output (C bits)
Data output (subcode Q)
Demodulation data input
DOUT/V pin
System
DI4
DI5
DI6
DI7
DI8
Format
EA
E9
E8
DIN1
DIN1
B0
L
L
L
L
0
1
0
B1
1
0
0
Run
L
CCB/SUB = low
B2
0
0
0
DIN2
DIN2
H
H
L
L
B3
LC8904Q
1
1
1
A0
0
0
0
A1
1
1
1
DIN3
DIN3
H
H
L
L
A2
1
1
1
A3
Stop
1
1
1
H
F9
F7
F8
DIN4
DIN4
H
H
H
H
B0
1
0
1
B1
1
0
0
CCB/SUB = high
B2
1
0
0
B3
0
1
1
A0
1
1
1
A1
1
1
1
No. 5014-13/20
A2
1
1
1
A3
1
1
1