MACH4-96 Lattice, MACH4-96 Datasheet - Page 10

• Manufacturer Part Number: MACH4-96
• Description: High-Performance EE CMOS Programmable Logic
• Manufacturer: Lattice

The Macrocell and Output Switch Matrix
Each M4-96/96 PAL block has 16 macrocells, half of which can drive I/O pins; this selection is made by
the output switch matrix. Each macrocell can drive one of four I/O cells. The allowed combinations are
shown in Table 1. Please refer to Figure 7 for macrocell and I/O pin numbers.The macrocells can be
configured as registered, latched, or combinatorial. In combination with the logic allocator, the registered
configuration can be any of the standard flip-flop types. The macrocell provides internal feedback
whether configured with or without the flip-flop, and whether or not the macrocell drives an I/O cell.
The flip-flop clock depends on the mode selected for the macrocell. In synchronous mode, any of
the PAL block clocks generated by the Clock Generator can be used. In asynchronous mode, the
additional choice of either edge of an individual product-term clock is available.
Initialization can be handled as part of a bank of macrocells via the PAL block initialization terms if in
synchronous mode, or individually if in asynchronous mode (Figure 4). In synchronous mode, one of
the PAL block product terms is available each for preset and reset. The swap function determines which
product term drives which function. This allows initialization polarity compatibility with the MACH 1
and 2 series. In asynchronous mode, one product term can be used either to drive reset or preset.
10
V A N T I S
From Logic Allocator
From PAL-Block
Clock Generator
Individual Clock
Product Term
Product Term
Initialization
From Logic
Product Terms
Individual
Allocator
Initialization
PAL-Clock
Individual macrocell resources
Generator
PAL-Block
Common PAL-block resource
From
Power-Up
Block CLK0
Block CLK1
Reset
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Power-Up
Reset
b. Asynchronous Mode
Figure 4. Macrocell
MACH4-96/96-15
SWAP
a. Synchronous Mode
D/T/L
AP
D/T/L
AP
AR
AR
Q
Q
To Output and Input
Switch Matrices
To Output and Input
Switch Matrices
21535A-4