QL4016 ETC, QL4016 Datasheet
QL4016
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QL4016 Summary of contents
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... QL4016 QuickRAM Data Sheet • • • • • • 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights High Performance & High Density 16,000 Usable PLD Gates with 118 I/Os • 300 MHz 16-bit Counters, 400 MHz • ...
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... RAM module has 1,152 RAM bits, for a total of 11,520 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) I/Os, the QL4016 is available in 84-pin PLCC, 100-pin TQFP, 100-pin CQFP and 144-pin TQFP packages. Designers can cascade multiple RAM modules to increase the depth or width allowed in ...
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... Input + logic cell + output total delays = under 6 ns • Data path speeds over 400 MHz • Counter speeds over 300 MHz • FIFO speeds over 160+ MHz • © 2002 QuickLogic Corporation QL4016 QuickRAM Data Sheet Rev I www.quicklogic.com • • • 3 • • • ...
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... QL4016 QuickRAM Data Sheet Rev I Electrical Specifications AC Characteristics calculate delays, multiply the appropriate K factor from following numbers in the tables provided. Symbol CLK t CWHI t CWLO t SET t RESET These limits are derived from a representative selection of the slowest paths through the Quick- RAM logic cell including typical net delays ...
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... Operating Range. © 2002 QuickLogic Corporation [8:0] WA [17:0] RCLK WCLK [1:0] MODE ASYNCRD Figure 4: QuickRAM Module Table 2: RAM Cell Synchronous Write Timing Parameter 1.0 0.0 1.0 0.0 1.0 0.0 a 5.0 Table 3: RAM Cell Synchronous Read Timing Parameter 1.0 0.0 1.0 0.0 a 4.0 QL4016 QuickRAM Data Sheet Rev I RE [8:0] [17:0] RD Propagation Delays (ns) Fanout 1.0 1.0 1.0 1.0 0.0 0.0 0.0 0.0 1.0 1.0 1.0 1.0 0.0 0.0 0.0 0.0 1.0 1.0 1.0 1.0 ...
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... QL4016 QuickRAM Data Sheet Rev I Symbol RPDRD a. Stated timing for worst case Propagation Delay over process variation Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. Symbol t High Drive Input Delay IN t High Drive Input, Inverting Delay ...
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... QuickLogic Corporation Table 7: I/O Cell Input Delays Parameter Table 8: I/O Cell Output Delays Propagation Delays (ns) Parameter Output Load Capacitance (pF) 3 2.1 2.2 1.2 1.6 a 2.0 a 1.2 Figure 5 (see ) PXZ tPHZ 5 pF Figure 5: Loads Used for t PXZ QL4016 QuickRAM Data Sheet Rev I Propagation Delays (ns) a Fanout 1.3 1.6 1.8 2.1 3.1 3.6 3.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 ...
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... QL4016 QuickRAM Data Sheet Rev I DC Characteristics The DC specifications are provided in the tables below. Parameter V Voltage CC V Voltage CCIO Input Voltage Latch-up Immunity Symbol V Supply Voltage CC V I/O Input Tolerance Voltage CCIO TA Ambient Temperature TC Case Temperature K Delay Factor • • • www.quicklogic.com 8 • ...
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... IOH = -12 mA IOH = -500 µA a IOL = 16 mA IOL = 1 GND CCIO GND CCIO GND VI, VIO = V or GND CCIO Contact Information QL4016 QuickRAM Data Sheet Rev I Min Max Units 0.5VCC VCCIO+0.5 V -0.5 0 2.4 V 0.9VCC V 0. -10 10 µ ...
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... QL4016 QuickRAM Data Sheet Rev I Kv and Kt Graphs 1.1000 1.0800 1.0600 1.0400 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 • • • www.quicklogic.com 10 • • • Voltage Factor vs. Supply Voltage 3 3.1 3.2 3.3 Supply Voltage (V) Figure 6: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 ...
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... CC MAX V CC 400 us Time Figure 8: Power-up Requirements when ramping the device. CC earlier than 400 µs can cause the device to behave improperly. and QL4016 QuickRAM Data Sheet Rev I Figure 500 mV. Deviation from CCIO CC MAX , as shown in . Figure 9 CCIO V CCIO IO Cells www ...
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... QL4016 QuickRAM Data Sheet Rev I JTAG TCK TMS TRSTB RDI Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges. One of these challenges concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149 ...
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... TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. © 2002 QuickLogic Corporation QL4016 QuickRAM Data Sheet Rev I The Extest instruction performs a PCB interconnect test. This test This instruction allows a device to remain in its The Bypass instruction allows data to skip a device's boundary • ...
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... QL4016 QuickRAM Data Sheet Rev I Pin Descriptions Pin Test Data In for JTAG /RAM init. TDI/RSI Serial Data In Active low Reset for JTAG /RAM TRSTB/RRO init. reset out TMS Test Mode Select for JTAG TCK Test Clock for JTAG Test data out for JTAG /RAM init. ...
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... TDI VCC GND I/O QL4016 QuickRAM Data Sheet Rev VCC 67 GCLK ACLK GND ...
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... QL4016 QuickRAM Data Sheet Rev I 100 TQFP/CQFP Pinout Diagram Pin 1 Pin 26 144 TQFP Pinout Diagram Pin 37 • • • www.quicklogic.com 16 • • • QuickRAM QL4016-1PF100C Figure 12: Top View of 100 Pin TQFP/CQFP Pin 1 QuickRAM QL4016-1PF144C Figure 13: Top View of 144 Pin TQFP Pin 76 ...
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... NC 102 NC GND 67 NC 103 NC I 104 I 105 NC I 106 I TRSTB 107 72 50 108 TMS 73 51 109 I 110 I/O QL4016 QuickRAM Data Sheet Rev I 53 111 78 I/O I/O 54 112 79 I/O I/O 55 113 80 I/O I/O 114 NC I/O VCC 115 81 VCC I/O 116 82 I/O I/O 56 117 83 I/O I/O 118 NC I/O I/O 57 119 ...
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... QL4016 QuickRAM Data Sheet Rev I Contact Information Telephone:408 990 4000 (US) E-mail: info@quicklogic.com Support:support@quicklogic.com Web site:http://www.quicklogic.com/ Revision History Revision Copyright Information Copyright © 2002 QuickLogic Corporation. All Rights Reserved. The information contained in this product brief, and the accompanying software programs are pro- tected by copyright ...